From: whitequark <whitequark@whitequark.org>
Date: Thu, 6 Feb 2020 14:48:48 +0000 (+0000)
Subject: hdl.mem: add synthesis attribute support.
X-Git-Tag: v0.2~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=31cd72c0b6250cb74e001df0e25a013bed17fdf2;p=nmigen.git

hdl.mem: add synthesis attribute support.

Fixes #291.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index dbddd61..0e5c93a 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -826,7 +826,7 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
                         memory = param_value
                         if memory not in memories:
                             memories[memory] = module.memory(width=memory.width, size=memory.depth,
-                                                             name=memory.name)
+                                                             name=memory.name, attrs=memory.attrs)
                             addr_bits = bits_for(memory.depth)
                             data_parts = []
                             data_mask = (1 << memory.width) - 1
diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py
index fc6c011..235cbd2 100644
--- a/nmigen/hdl/mem.py
+++ b/nmigen/hdl/mem.py
@@ -1,4 +1,5 @@
 import operator
+from collections import OrderedDict
 
 from .. import tracer
 from .ast import *
@@ -24,14 +25,17 @@ class Memory:
     name : str
         Name hint for this memory. If ``None`` (default) the name is inferred from the variable
         name this ``Signal`` is assigned to.
+    attrs : dict
+        Dictionary of synthesis attributes.
 
     Attributes
     ----------
     width : int
     depth : int
     init : list of int
+    attrs : dict
     """
-    def __init__(self, *, width, depth, init=None, name=None, simulate=True):
+    def __init__(self, *, width, depth, init=None, name=None, attrs=None, simulate=True):
         if not isinstance(width, int) or width < 0:
             raise TypeError("Memory width must be a non-negative integer, not {!r}"
                             .format(width))
@@ -44,6 +48,7 @@ class Memory:
 
         self.width = width
         self.depth = depth
+        self.attrs = OrderedDict(() if attrs is None else attrs)
 
         # Array of signals for simulation.
         self._array = Array()
diff --git a/nmigen/test/test_hdl_mem.py b/nmigen/test/test_hdl_mem.py
index e7fc232..131c639 100644
--- a/nmigen/test/test_hdl_mem.py
+++ b/nmigen/test/test_hdl_mem.py
@@ -42,6 +42,12 @@ class MemoryTestCase(FHDLTestCase):
                     "'str' object cannot be interpreted as an integer"):
             m = Memory(width=8, depth=4, init=[1, "0"])
 
+    def test_attrs(self):
+        m1 = Memory(width=8, depth=4)
+        self.assertEqual(m1.attrs, {})
+        m2 = Memory(width=8, depth=4, attrs={"ram_block": True})
+        self.assertEqual(m2.attrs, {"ram_block": True})
+
     def test_read_port_transparent(self):
         mem    = Memory(width=8, depth=4)
         rdport = mem.read_port()