From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 9 Jul 2020 08:32:55 +0000 (+0100)
Subject: make carry output handling optional in common output stage
X-Git-Tag: div_pipeline~142
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=31d1f5273eaaf72044b68d90c3d6242515fdd445;p=soc.git

make carry output handling optional in common output stage
---

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index 96de016b..cddf311f 100644
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -32,9 +32,12 @@ class CommonOutputStage(PipeModBase):
         with m.Else():
             comb += target.eq(o)
 
-        # Handle carry_out
-        comb += self.o.xer_ca.data.eq(self.i.xer_ca.data)
-        comb += self.o.xer_ca.ok.eq(op.output_carry)
+        # carry-out only if actually present in this input spec
+        # (note: MUL and DIV do not have it, but ALU and Logical do)
+        if hasattr(self.i.xer_ca):
+            # Handle carry_out
+            comb += self.o.xer_ca.data.eq(self.i.xer_ca.data)
+            comb += self.o.xer_ca.ok.eq(op.output_carry)
 
         # create condition register cr0 and sticky-overflow
         is_nzero = Signal(reset_less=True)