From: lkcl <lkcl@web>
Date: Wed, 19 Apr 2023 13:14:34 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=31d9e45ea600bb24d0ce85e9a7f1581ddcf1d87c;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index d271cf96a..59e0e36fb 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -144,19 +144,28 @@ to the order in which VL and SUBVL loops are applied being swapped
 
 ### Core concept loop
 
+This example illustrates the Cray-style Loop concept. However where most Cray
+Vectors have a Max Vector Length hard-coded into the architecture, Simple-V
+allows MVL to be set, but only as a static immediate, so that compilers may
+embed the register resource allocation statically at compile-time.
+
 ```
 loop:
     setvl a3, a0, MVL=8    #  update a3 with vl
                            # (# of elements this iteration)
-                           # set MVL to 8
+                           # set MVL to 8 and
+                           # set a3=VL=MIN(a0,MVL)
     # do vector operations at up to 8 length (MVL=8)
     # ...
-    sub a0, a0, a3   # Decrement count by vl
+    sub. a0, a0, a3   # Decrement count by vl, set CR0.eq
     bnez a0, loop    # Any more?
 ```
 
 ### Loop using Rc=1
 
+In this example, the `setvl.` instruction enabled Rc=1, which
+sets CR0.eq when VL becomes zero.
+
 ```
     my_fn:
       li r3, 1000