From: Matthew Malcomson Date: Thu, 9 May 2019 09:29:24 +0000 (+0100) Subject: [binutils][aarch64] New SVE_Zm4_11_INDEX operand. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=31e36ab341498bb477a46a0475100ec5d471c4f2;p=binutils-gdb.git [binutils][aarch64] New SVE_Zm4_11_INDEX operand. This includes defining a new single bit field SVE_i2h at position 20. SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16. gas/ChangeLog: 2019-05-09 Matthew Malcomson * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm4_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. (fields): Handle SVE_i2h field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 4e968452e93..9e08aef8d3a 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2019-05-09 Matthew Malcomson + + * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX + operand. + 2019-05-09 Matthew Malcomson * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22 diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 7bf73fd9c3c..5193c5d8e86 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -5655,6 +5655,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zm3_INDEX: case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: reg_type = REG_TYPE_ZN; diff --git a/include/ChangeLog b/include/ChangeLog index 65cdf2b6d2b..f9650c805b4 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2019-05-09 Matthew Malcomson + + * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand. + 2019-05-09 Matthew Malcomson * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index d1d366b439c..25201cf1899 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -415,6 +415,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */ + AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8e8614206cb..b020582dd12 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2019-05-09 Matthew Malcomson + + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking + for SVE_Zm4_11_INDEX. + (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. + (fields): Handle SVE_i2h field. + * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. + * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. + 2019-05-09 Matthew Malcomson * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 00ab9b370ed..b2a101feca9 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -647,8 +647,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 191: case 192: case 193: - case 198: - case 201: + case 199: + case 202: return aarch64_ins_regno (self, info, code, inst, errors); case 14: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 204: + case 205: return aarch64_ins_reglane (self, info, code, inst, errors); case 35: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -704,7 +704,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 182: case 183: case 184: - case 203: + case 204: return aarch64_ins_imm (self, info, code, inst, errors); case 43: case 44: @@ -851,11 +851,12 @@ aarch64_insert_operand (const aarch64_operand *self, case 195: case 196: case 197: + case 198: return aarch64_ins_sve_quad_index (self, info, code, inst, errors); - case 199: - return aarch64_ins_sve_index (self, info, code, inst, errors); case 200: - case 202: + return aarch64_ins_sve_index (self, info, code, inst, errors); + case 201: + case 203: return aarch64_ins_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index d70a29095bf..16faf593a57 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -20078,8 +20078,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 191: case 192: case 193: - case 198: - case 201: + case 199: + case 202: return aarch64_ext_regno (self, info, code, inst, errors); case 9: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -20095,7 +20095,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 204: + case 205: return aarch64_ext_reglane (self, info, code, inst, errors); case 35: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -20140,7 +20140,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 182: case 183: case 184: - case 203: + case 204: return aarch64_ext_imm (self, info, code, inst, errors); case 43: case 44: @@ -20289,11 +20289,12 @@ aarch64_extract_operand (const aarch64_operand *self, case 195: case 196: case 197: + case 198: return aarch64_ext_sve_quad_index (self, info, code, inst, errors); - case 199: - return aarch64_ext_sve_index (self, info, code, inst, errors); case 200: - case 202: + return aarch64_ext_sve_index (self, info, code, inst, errors); + case 201: + case 203: return aarch64_ext_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 3c0e13a0fb9..4aec8709384 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -221,6 +221,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 84e30f5f345..fac71118f5e 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -296,6 +296,7 @@ const aarch64_field fields[] = { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */ { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */ { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */ + { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */ { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */ { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */ { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */ @@ -1519,6 +1520,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_Zm3_INDEX: case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: size = get_operand_fields_width (get_operand_from_code (type)); shift = get_operand_specific_data (&aarch64_operands[type]); @@ -3324,6 +3326,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm3_INDEX: case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno, diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 8d181759288..bb0a50892b2 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -123,6 +123,7 @@ enum aarch64_field_kind FLD_SVE_i3h, FLD_SVE_i3l, FLD_SVE_i3h2, + FLD_SVE_i2h, FLD_SVE_imm3, FLD_SVE_imm4, FLD_SVE_imm5, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 6f8f47a664d..d45c2f663db 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4969,6 +4969,9 @@ struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sve_quad_index, "SVE_Zm3_11_INDEX", \ 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3), \ "an indexed SVE vector register") \ + Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", \ + 4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4), \ + "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \ 4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ "an indexed SVE vector register") \