From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 Jun 2018 05:48:26 +0000 (+0100)
Subject: add images
X-Git-Tag: convert-csv-opcode-to-binary~5316
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=31f81abf44e1c95f7b4e322977e363c7adfe67ea;p=libreriscv.git

add images
---

diff --git a/simple_v_extension/padd9_alu1.png b/simple_v_extension/padd9_alu1.png
new file mode 100644
index 000000000..330c55e4c
Binary files /dev/null and b/simple_v_extension/padd9_alu1.png differ
diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index fc49acb64..d6269b489 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -170,7 +170,15 @@
 % but MODIFYING the remaining "vectorised" op, subtracting the now
 % scalar ops from it.
 
-\frame{\frametitle{Predicated 8-parallel ADD: optimised (not masked)}
+\frame{\frametitle{Predicated 8-parallel ADD: 1-wide ALU}
+ \begin{center}
+  \includegraphics[height=2.5in]{padd9_alu1.png}\\
+  {\bf \red Predicated adds are shuffled down: 6 cycles in total}
+ \end{center}
+}
+
+
+\frame{\frametitle{Predicated 8-parallel ADD: 4-wide ALU}
  \begin{center}
   \includegraphics[height=2.5in]{padd9_alu4.png}\\
   {\bf \red Predicated adds are shuffled down: 4 in 1st cycle, 2 in 2nd}