From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 27 Feb 2006 21:33:11 +0000 (-0500)
Subject: Fixes so that it compiles properly. Still working on .py file issues.
X-Git-Tag: m5_2.0_beta1~212
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=31fc398f0641a9dcc9757520e9dc7fd2cce102fb;p=gem5.git

Fixes so that it compiles properly. Still working on .py file issues.

SConscript:
    Add Back memory to be built
mem/physical.hh:
    Fix function declerations
python/m5/objects/BaseCPU.py:
    Remove IL1 and DL1 params from the cpu object

--HG--
extra : convert_revision : 2f285dc626bc8d84d095def68e986fe7e6f3d8e9
---

diff --git a/SConscript b/SConscript
index 078b1e831..1c13a9307 100644
--- a/SConscript
+++ b/SConscript
@@ -91,6 +91,7 @@ base_sources = Split('''
 	cpu/static_inst.cc
         cpu/sampler/sampler.cc
 
+        mem/memory.cc
         mem/page_table.cc
         mem/physical.cc
         mem/port.cc
diff --git a/mem/physical.hh b/mem/physical.hh
index fb2d0d743..90515d7d1 100644
--- a/mem/physical.hh
+++ b/mem/physical.hh
@@ -70,9 +70,9 @@ class PhysicalMemory : public Memory
 
     std::map<std::string, MemoryPort*> memoryPortList;
 
-    Port * PhysicalMemory::getPort(const char *if_name);
+    virtual Port * getPort(const char *if_name);
 
-    Port * addPort(std::string portName);
+    virtual Port * addPort(std::string portName);
 
     int numPorts;
 
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py
index fac452285..e5e43022f 100644
--- a/python/m5/objects/BaseCPU.py
+++ b/python/m5/objects/BaseCPU.py
@@ -2,8 +2,6 @@ from m5 import *
 class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True
-    icache = Param.BaseMem(NULL, "L1 instruction cache object")
-    dcache = Param.BaseMem(NULL, "L1 data cache object")
 
     if build_env['FULL_SYSTEM']:
         dtb = Param.AlphaDTB("Data TLB")