From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 6 Apr 2018 16:45:03 +0000 (+0100)
Subject: partial update
X-Git-Tag: convert-csv-opcode-to-binary~5746
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3213163ec570d30687aae4fb8c6d07d6dde65a7e;p=libreriscv.git

partial update
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 4085d7b59..9cb80ab9a 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -105,6 +105,20 @@ to keep ALU pipelines 100% occupied.
 This very simple proposal offers a way to increase pipeline activity in the
 one key area which really matters: the inner loop.
 
+## Conclusions
+
+In the above sections the four different ways where parallel instruction
+execution has closely and loosely inter-related implications for the ISA and
+for implementors, were outlined.  The pluses and minuses came out as
+follows:
+
+* Fixed vs variable parallelism: <b>variable</b>
+* Implicit (indirect) vs fixed (integral) instruction bit-width: <b>indirect</b>
+* Implicit vs explicit type-conversion: <b>explicit</b>
+* Implicit vs explicit inner loops: <b>implicit</b>
+
+
+
 # References
 
 * SIMD considered harmful <https://www.sigarch.org/simd-instructions-considered-harmful/>