From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 15 Feb 2022 20:07:35 +0000 (+0000)
Subject: for *write* the counter-address on downconvert was correct
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3214e37140a097173de9a1fe6bf71280f6478b93;p=soc.git

for *write* the counter-address on downconvert was correct
but for *read* it has to be pre-advanced (if that makes any sense)
---

diff --git a/src/soc/bus/wb_downconvert.py b/src/soc/bus/wb_downconvert.py
index 2b03d56b..fbf8239f 100644
--- a/src/soc/bus/wb_downconvert.py
+++ b/src/soc/bus/wb_downconvert.py
@@ -73,8 +73,7 @@ class WishboneDownConvert(Elaboratable):
                     comb += slave.cyc.eq(1)
                     comb += slave.stb.eq(1)
                     with m.If(slave.ack | skip):
-                        comb += cur_counter.eq(counter + 1) # TODO use Picker
-                        sync += counter.eq(cur_counter)
+                        sync += counter.eq(counter + 1)
                         with m.If(counter_done):
                             comb += master.ack.eq(1)
                             m.next = "IDLE"