From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Tue, 12 Mar 2019 04:13:01 +0000 (-0700)
Subject: Remove whitespace
X-Git-Tag: div_pipeline~2306
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=321ca5c266582a3e3cdccec52c8f5f924004813a;p=soc.git

Remove whitespace
---

diff --git a/TLB/src/RegisterFile.py b/TLB/src/RegisterFile.py
index 5fd691c8..7cc00bc2 100644
--- a/TLB/src/RegisterFile.py
+++ b/TLB/src/RegisterFile.py
@@ -3,38 +3,38 @@ from nmigen.lib.coding import Decoder
 
 class RegisterFile():
     """ Register File
-        
+
         The purpose of this module is to represent a bank of registers.
-        
+
         Usage:
         To Write: Set the address line to the desired register in the file, set
         write_enable HIGH, and wait one cycle
         To Read: Set the address line to the desired register in the file, set
         write_enable LOW, and wait one cycle. 
     """
-    
+
     def __init__(self, data_size, file_size):
         """ Arguments:
             * data_size: (bit count) The number of bits in one register
             * cam_size: (entry count) the number of registers in this file
         """
-        
+
         # Internal
         self.register_array = Array(Signal(data_size) for x in range(file_size))
-        
+
         # Input
         self.enable = Signal(1)
         self.write_enable = Signal(1)
         self.address = Signal(max=file_size)
         self.data_i = Signal(data_size)
-        
+
         # Output
         self.valid = Signal(1)
         self.data_o = Signal(data_size)
-        
+
     def elaborate(self, platform=None):
         m = Module()
-        
+
         with m.If(self.enable):
             # Write Logic
             with m.If(self.write_enable):
@@ -54,6 +54,6 @@ class RegisterFile():
             m.d.sync += [
                 self.valid.eq(0),
                 self.data_o.eq(0)
-            ]            
-        
-        return m
\ No newline at end of file
+            ]
+
+        return m
diff --git a/TLB/test/test_register_file.py b/TLB/test/test_register_file.py
index ee8b172d..177912ec 100644
--- a/TLB/test/test_register_file.py
+++ b/TLB/test/test_register_file.py
@@ -14,21 +14,21 @@ def setRegisterFile(dut, e, we, a, di):
     yield dut.address.eq(a)
     yield dut.data_i.eq(di)
     yield
- 
+
 # Checks the address output of the Cam
 # Arguments:
 #   dut: The Cam being tested
 #   v (Valid): If the output is valid or not
-#   op (Operation): (0 => ==), (1 => !=)   
+#   op (Operation): (0 => ==), (1 => !=)
 def check_valid(dut, v, op):
     out_v = yield dut.valid
     assert_op("Valid", out_v, v, op)
- 
+
 # Checks the address output of the Cam
 # Arguments:
 #   dut: The Cam being tested
 #   do (Data Out): The current output data
-#   op (Operation): (0 => ==), (1 => !=)   
+#   op (Operation): (0 => ==), (1 => !=)
 def check_data(dut, do, op):
     out_do = yield dut.data_o
     assert_op("Data Out", out_do, do, op)
@@ -54,8 +54,8 @@ def testbench(dut):
     yield from setRegisterFile(dut, enable, write_enable, address, data)
     yield
     yield from check_all(dut, valid, 0, 0, 0)
-    
-    # Test read 0 
+
+    # Test read 0
     enable = 1
     write_enable = 0
     address = 0
@@ -63,8 +63,8 @@ def testbench(dut):
     valid = 1
     yield from setRegisterFile(dut, enable, write_enable, address, data)
     yield
-    yield from check_all(dut, valid, data, 0, 0) 
-    
+    yield from check_all(dut, valid, data, 0, 0)
+
     # Test write 3
     enable = 1
     write_enable = 1
@@ -74,8 +74,8 @@ def testbench(dut):
     yield from setRegisterFile(dut, enable, write_enable, address, data)
     yield
     yield from check_all(dut, valid, 0, 0, 0)
-    
-    # Test read 3  
+
+    # Test read 3
     enable = 1
     write_enable = 0
     address = 3
@@ -83,9 +83,9 @@ def testbench(dut):
     valid = 1
     yield from setRegisterFile(dut, enable, write_enable, address, data)
     yield
-    yield from check_all(dut, valid, data, 0, 0)    
-    
-    # Test read 0 
+    yield from check_all(dut, valid, data, 0, 0)
+
+    # Test read 0
     enable = 1
     write_enable = 0
     address = 0
@@ -93,8 +93,8 @@ def testbench(dut):
     valid = 1
     yield from setRegisterFile(dut, enable, write_enable, address, data)
     yield
-    yield from check_all(dut, valid, data, 0, 0)   
-    
+    yield from check_all(dut, valid, data, 0, 0)
+
     # Test overwrite 0
     enable = 1
     write_enable = 1
@@ -103,9 +103,9 @@ def testbench(dut):
     valid = 0
     yield from setRegisterFile(dut, enable, write_enable, address, data)
     yield
-    yield from check_all(dut, valid, 0, 0, 0)  
-    
-    # Test read 0 
+    yield from check_all(dut, valid, 0, 0, 0)
+
+    # Test read 0
     enable = 1
     write_enable = 0
     address = 0
@@ -113,10 +113,9 @@ def testbench(dut):
     valid = 1
     yield from setRegisterFile(dut, enable, write_enable, address, data)
     yield
-    yield from check_all(dut, valid, data, 0, 0)     
-    
+    yield from check_all(dut, valid, data, 0, 0)
 
 if __name__ == "__main__":
     dut = RegisterFile(4, 4)
     run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_register_file.vcd")
-    print("RegisterFile Unit Test Success")
\ No newline at end of file
+    print("RegisterFile Unit Test Success")