From: David Shah Date: Fri, 22 Feb 2019 12:12:10 +0000 (+0000) Subject: versa_ecp5: Remove negative diff IO pins X-Git-Tag: 24jan2021_ls180~1390^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=321dd8fcf6586bc88806cae61f1538756cde8eb4;p=litex.git versa_ecp5: Remove negative diff IO pins In Lattice FPGAs only the positive side of differential pairs should be specified (unlike Xilinx) These are a warning on Diamond (which trims unused IO) and an error with Yosys/nextpnr (which doesn't so they conflict when the positive pin is 'expanded'). Already this is the case for the clock input, this commit performs the same change for the DDR3 pins. --- diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py index dbfc26cf..7d11e470 100644 --- a/litex/boards/platforms/versa_ecp5.py +++ b/litex/boards/platforms/versa_ecp5.py @@ -50,9 +50,7 @@ _io = [ IOStandard("SSTL135_I"), Misc("TERMINATION=75")), Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")), - Subsignal("dqs_n", Pins("J1 G5"), IOStandard("SSTL135D_I")), Subsignal("clk_p", Pins("M4"), IOStandard("SSTL135D_I")), - Subsignal("clk_n", Pins("N5"), IOStandard("SSTL135D_I")), Subsignal("cke", Pins("N2"), IOStandard("SSTL135_I")), Subsignal("odt", Pins("L2"), IOStandard("SSTL135_I")), Subsignal("reset_n", Pins("N4"), IOStandard("SSTL135_I")),