From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 22 Mar 2022 13:43:18 +0000 (+0100)
Subject: Proper SigBit forming in sim
X-Git-Tag: yosys-0.16~32
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=322ab1cd54f4cddba4e9408887ed822c541185f9;p=yosys.git

Proper SigBit forming in sim
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index b56ccb987..8081ffffe 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1708,13 +1708,13 @@ struct AIWWriter : public OutputWriter
 			if (index < w->start_offset || index > w->start_offset + w->width)
 				log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
 			if (type == "input") {
-				aiw_inputs[variable] = SigBit(w,index);
+				aiw_inputs[variable] = SigBit(w,index-w->start_offset);
 			} else if (type == "init") {
-				aiw_inits[variable] = SigBit(w,index);
+				aiw_inits[variable] = SigBit(w,index-w->start_offset);
 			} else if (type == "latch") {
-				aiw_latches[variable] = {SigBit(w,index), false};
+				aiw_latches[variable] = {SigBit(w,index-w->start_offset), false};
 			} else if (type == "invlatch") {
-				aiw_latches[variable] = {SigBit(w,index), true};
+				aiw_latches[variable] = {SigBit(w,index-w->start_offset), true};
 			}
 		}