From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Jun 2018 17:45:11 +0000 (+0100)
Subject: add ddr3 ohwr link
X-Git-Tag: convert-csv-opcode-to-binary~5084
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=324e009dd199361d5c84e6a15dca1b1be24a6b94;p=libreriscv.git

add ddr3 ohwr link
---

diff --git a/shakti/m_class/DDR.mdwn b/shakti/m_class/DDR.mdwn
index 8bae234cc..8607cddf1 100644
--- a/shakti/m_class/DDR.mdwn
+++ b/shakti/m_class/DDR.mdwn
@@ -1,3 +1,4 @@
 # DDR (DRAM) Controller and PHY
 
 * <https://github.com/enjoy-digital/litedram> - controller inc. DDR3 / LPDDR3
+* <https://www.ohwr.org/projects/ddr3-sp6-core/wiki/wiki> - CERN DDR3 ctrl