From: Jason Ekstrand <jason@jlekstrand.net>
Date: Wed, 18 Mar 2020 18:29:06 +0000 (-0500)
Subject: anv: Only add END_OF_PIPE_SYNC if we actually have AUX_INVAL
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3252041a7872c49e53bb02ffe8b079b5fc43f15e;p=mesa.git

anv: Only add END_OF_PIPE_SYNC if we actually have AUX_INVAL

Fixes: 43dc842cb91c "anv: Wait for the GPU to be idle before..."
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: D Scott Phillips <d.scott.phillips@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234>
---

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index c60d156d522..2c5a448aff3 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2042,7 +2042,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
     *    add extra flushes in the case it knows that the engine is already
     *    IDLE."
     */
-   if (GEN_GEN == 12 && ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
+   if (GEN_GEN == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT))
       bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
 
    /* If we're going to do an invalidate and we have a pending end-of-pipe