From: Nick Clifton Date: Mon, 9 Feb 2004 12:15:57 +0000 (+0000) Subject: Add support for relaxing the 32bit ldc/stc instructions. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3255318a047df68f30a4514400fdfbfac114d36d;p=binutils-gdb.git Add support for relaxing the 32bit ldc/stc instructions. --- diff --git a/bfd/ChangeLog b/bfd/ChangeLog index cbd41d03c1c..81c80d3f2b2 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,8 @@ +2004-02-09 Anil Paranjpe + + * coff-h8300.c: Added comments about relaxation for ldc.w and stc.w. + * elf32-h8300.c: Likewise. + 2004-02-09 Christian Vogel Nick Clifton diff --git a/bfd/coff-h8300.c b/bfd/coff-h8300.c index bd798a64b65..e4d1399e31f 100644 --- a/bfd/coff-h8300.c +++ b/bfd/coff-h8300.c @@ -780,8 +780,8 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, instructions: "band", "bclr", "biand", "bild", "bior", "bist", "bixor", - "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and - "mov.[bwl]" + "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", "ldc.w", + "stc.w" and "mov.[bwl]" We may relax this into an 16-bit absolute address if it's in the right range. */ diff --git a/bfd/elf32-h8300.c b/bfd/elf32-h8300.c index 1a176214f01..547adfaa935 100644 --- a/bfd/elf32-h8300.c +++ b/bfd/elf32-h8300.c @@ -1198,7 +1198,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, "band", "bclr", "biand", "bild", "bior", "bist", "bixor", "bld", "bnot", "bor", "bset", "bst", "btst", - "bxor", and "mov.[bwl]" + "bxor", "ldc.w", "stc.w" and "mov.[bwl]" We may relax this into an 16-bit absolute address if it's in the right range. */ diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 8f0d6d76359..438c6d8ad11 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2004-02-09 Anil Paranjpe + + * h8300.h (32bit ldc/stc): Add relaxing support. + 2004-01-12 Anil Paranjpe * h8300.h (BITOP): Pass MEMRELAX flag. diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h index 76d42e58a72..29374df5b4f 100644 --- a/include/opcode/h8300.h +++ b/include/opcode/h8300.h @@ -1434,8 +1434,9 @@ struct h8_opcode h8_opcodes[] = {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | ABS32LIST, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | ABS32LIST, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, + {O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}}, @@ -1809,8 +1810,8 @@ struct h8_opcode h8_opcodes[] = {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | ABS32LIST, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | ABS32LIST, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, {O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}}, diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index 7458855d057..f67c5ecf6bd 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2004-02-09 Anil Paranjpe + + * ld-h8300/relax-5.s: New file: Source for relax-5 test. + * ld-h8300/relax-5.d: New file: Expected output and commands for + assembling and linking the relax-5 test. + * ld-h8300/relax-5-coff.d: New file: Variant for the COFF based + toolchain. + * ld-h8300/h8300-exp: Run the relax-5 test. + 2004-01-23 Daniel Jacobowitz * ld-arm/arm-app-abs32.s, ld-arm/arm-app-abs32.r, diff --git a/ld/testsuite/ld-h8300/h8300.exp b/ld/testsuite/ld-h8300/h8300.exp index a8e8ddaf60d..a063f4e1cdf 100644 --- a/ld/testsuite/ld-h8300/h8300.exp +++ b/ld/testsuite/ld-h8300/h8300.exp @@ -30,7 +30,9 @@ if {[istarget *-elf]} { run_dump_test relax-2 run_dump_test relax-3 run_dump_test relax-4 + run_dump_test relax-5 } else { run_dump_test relax-3-coff run_dump_test relax-4-coff + run_dump_test relax-5-coff } diff --git a/ld/testsuite/ld-h8300/relax-5-coff.d b/ld/testsuite/ld-h8300/relax-5-coff.d new file mode 100644 index 00000000000..dae5d2344f4 --- /dev/null +++ b/ld/testsuite/ld-h8300/relax-5-coff.d @@ -0,0 +1,50 @@ +# name: H8300 Relaxation Test 5 +# source: relax-5.s +# ld: --relax -m h8300s +# objdump: -d --no-show-raw-insn + +.*: file format .*-h8300 + +Disassembly of section .text: + +00000100 <_start>: + 100: 01 40 6b 00 00 00 ldc @0x0:16,ccr + 106: 01 40 6b 00 7f ff ldc @0x7fff:16,ccr + 10c: 01 40 6b 20 00 00 80 00 ldc @0x8000:32,ccr + 114: 01 40 6b 20 00 00 ff 00 ldc @0xff00:32,ccr + 11c: 01 40 6b 20 00 ff ff 00 ldc @0xffff00:32,ccr + 124: 01 40 6b 20 ff ff 7f ff ldc @0xffff7fff:32,ccr + 12c: 01 40 6b 00 80 00 ldc @0x8000:16,ccr + 132: 01 40 6b 00 fe ff ldc @0xfeff:16,ccr + 138: 01 40 6b 00 ff 00 ldc @0xff00:16,ccr + 13e: 01 40 6b 00 ff ff ldc @0xffff:16,ccr + 144: 01 40 6b 80 00 00 stc ccr,@0x0:16 + 14a: 01 40 6b 80 7f ff stc ccr,@0x7fff:16 + 150: 01 40 6b a0 00 00 80 00 stc ccr,@0x8000:32 + 158: 01 40 6b a0 00 00 ff 00 stc ccr,@0xff00:32 + 160: 01 40 6b a0 00 ff ff 00 stc ccr,@0xffff00:32 + 168: 01 40 6b a0 ff ff 7f ff stc ccr,@0xffff7fff:32 + 170: 01 40 6b 80 80 00 stc ccr,@0x8000:16 + 176: 01 40 6b 80 fe ff stc ccr,@0xfeff:16 + 17c: 01 40 6b 80 ff 00 stc ccr,@0xff00:16 + 182: 01 40 6b 80 ff ff stc ccr,@0xffff:16 + 188: 01 41 6b 00 00 00 ldc @0x0:16,exr + 18e: 01 41 6b 00 7f ff ldc @0x7fff:16,exr + 194: 01 41 6b 20 00 00 80 00 ldc @0x8000:32,exr + 19c: 01 41 6b 20 00 00 ff 00 ldc @0xff00:32,exr + 1a4: 01 41 6b 20 00 ff ff 00 ldc @0xffff00:32,exr + 1ac: 01 41 6b 20 ff ff 7f ff ldc @0xffff7fff:32,exr + 1b4: 01 41 6b 00 80 00 ldc @0x8000:16,exr + 1ba: 01 41 6b 00 fe ff ldc @0xfeff:16,exr + 1c0: 01 41 6b 00 ff 00 ldc @0xff00:16,exr + 1c6: 01 41 6b 00 ff ff ldc @0xffff:16,exr + 1cc: 01 41 6b 80 00 00 stc exr,@0x0:16 + 1d2: 01 41 6b 80 7f ff stc exr,@0x7fff:16 + 1d8: 01 41 6b a0 00 00 80 00 stc exr,@0x8000:32 + 1e0: 01 41 6b a0 00 00 ff 00 stc exr,@0xff00:32 + 1e8: 01 41 6b a0 00 ff ff 00 stc exr,@0xffff00:32 + 1f0: 01 41 6b a0 ff ff 7f ff stc exr,@0xffff7fff:32 + 1f8: 01 41 6b 80 80 00 stc exr,@0x8000:16 + 1fe: 01 41 6b 80 fe ff stc exr,@0xfeff:16 + 204: 01 41 6b 80 ff 00 stc exr,@0xff00:16 + 20a: 01 41 6b 80 ff ff stc exr,@0xffff:16 diff --git a/ld/testsuite/ld-h8300/relax-5.d b/ld/testsuite/ld-h8300/relax-5.d new file mode 100644 index 00000000000..d33eb0fa485 --- /dev/null +++ b/ld/testsuite/ld-h8300/relax-5.d @@ -0,0 +1,50 @@ +# name: H8300 Relaxation Test 5 +# source: relax-5.s +# ld: --relax -m h8300self +# objdump: -d --no-show-raw-insn + +.*: file format .*-h8300 + +Disassembly of section .text: + +00000100 <_start>: + 100: 01 40 6b 00 00 00 ldc @0x0:16,ccr + 106: 01 40 6b 00 7f ff ldc @0x7fff:16,ccr + 10c: 01 40 6b 20 00 00 80 00 ldc @0x8000:32,ccr + 114: 01 40 6b 20 00 00 ff 00 ldc @0xff00:32,ccr + 11c: 01 40 6b 20 00 ff ff 00 ldc @0xffff00:32,ccr + 124: 01 40 6b 20 ff ff 7f ff ldc @0xffff7fff:32,ccr + 12c: 01 40 6b 00 80 00 ldc @0x8000:16,ccr + 132: 01 40 6b 00 fe ff ldc @0xfeff:16,ccr + 138: 01 40 6b 00 ff 00 ldc @0xff00:16,ccr + 13e: 01 40 6b 00 ff ff ldc @0xffff:16,ccr + 144: 01 40 6b 80 00 00 stc ccr,@0x0:16 + 14a: 01 40 6b 80 7f ff stc ccr,@0x7fff:16 + 150: 01 40 6b a0 00 00 80 00 stc ccr,@0x8000:32 + 158: 01 40 6b a0 00 00 ff 00 stc ccr,@0xff00:32 + 160: 01 40 6b a0 00 ff ff 00 stc ccr,@0xffff00:32 + 168: 01 40 6b a0 ff ff 7f ff stc ccr,@0xffff7fff:32 + 170: 01 40 6b 80 80 00 stc ccr,@0x8000:16 + 176: 01 40 6b 80 fe ff stc ccr,@0xfeff:16 + 17c: 01 40 6b 80 ff 00 stc ccr,@0xff00:16 + 182: 01 40 6b 80 ff ff stc ccr,@0xffff:16 + 188: 01 41 6b 00 00 00 ldc @0x0:16,exr + 18e: 01 41 6b 00 7f ff ldc @0x7fff:16,exr + 194: 01 41 6b 20 00 00 80 00 ldc @0x8000:32,exr + 19c: 01 41 6b 20 00 00 ff 00 ldc @0xff00:32,exr + 1a4: 01 41 6b 20 00 ff ff 00 ldc @0xffff00:32,exr + 1ac: 01 41 6b 20 ff ff 7f ff ldc @0xffff7fff:32,exr + 1b4: 01 41 6b 00 80 00 ldc @0x8000:16,exr + 1ba: 01 41 6b 00 fe ff ldc @0xfeff:16,exr + 1c0: 01 41 6b 00 ff 00 ldc @0xff00:16,exr + 1c6: 01 41 6b 00 ff ff ldc @0xffff:16,exr + 1cc: 01 41 6b 80 00 00 stc exr,@0x0:16 + 1d2: 01 41 6b 80 7f ff stc exr,@0x7fff:16 + 1d8: 01 41 6b a0 00 00 80 00 stc exr,@0x8000:32 + 1e0: 01 41 6b a0 00 00 ff 00 stc exr,@0xff00:32 + 1e8: 01 41 6b a0 00 ff ff 00 stc exr,@0xffff00:32 + 1f0: 01 41 6b a0 ff ff 7f ff stc exr,@0xffff7fff:32 + 1f8: 01 41 6b 80 80 00 stc exr,@0x8000:16 + 1fe: 01 41 6b 80 fe ff stc exr,@0xfeff:16 + 204: 01 41 6b 80 ff 00 stc exr,@0xff00:16 + 20a: 01 41 6b 80 ff ff stc exr,@0xffff:16 diff --git a/ld/testsuite/ld-h8300/relax-5.s b/ld/testsuite/ld-h8300/relax-5.s new file mode 100644 index 00000000000..b5afedbfcca --- /dev/null +++ b/ld/testsuite/ld-h8300/relax-5.s @@ -0,0 +1,66 @@ +; Relaxation is possible from @aa:32 to @aa:16 for following instructions +; ldc.w @@aa:32,ccr +; stc.w ccr,@@aa:32 +; ldc.w @aa:32,exr +; stc.w exr,@aa:32 + .h8300s + .globl _start +; +; Relaxation of aa:32 +; + _start: + ldc @s1:32,ccr + ldc @s2:32,ccr + ldc @s3:32,ccr + ldc @s4:32,ccr + ldc @s5:32,ccr + ldc @s6:32,ccr + ldc @s7:32,ccr + ldc @s8:32,ccr + ldc @s9:32,ccr + ldc @s10:32,ccr + + stc ccr,@s1:32 + stc ccr,@s2:32 + stc ccr,@s3:32 + stc ccr,@s4:32 + stc ccr,@s5:32 + stc ccr,@s6:32 + stc ccr,@s7:32 + stc ccr,@s8:32 + stc ccr,@s9:32 + stc ccr,@s10:32 + + ldc @s1:32,exr + ldc @s2:32,exr + ldc @s3:32,exr + ldc @s4:32,exr + ldc @s5:32,exr + ldc @s6:32,exr + ldc @s7:32,exr + ldc @s8:32,exr + ldc @s9:32,exr + ldc @s10:32,exr + + stc exr,@s1:32 + stc exr,@s2:32 + stc exr,@s3:32 + stc exr,@s4:32 + stc exr,@s5:32 + stc exr,@s6:32 + stc exr,@s7:32 + stc exr,@s8:32 + stc exr,@s9:32 + stc exr,@s10:32 + + .equ s1,0 + .equ s2,0x7fff + .equ s3,0x8000 + .equ s4,0xff00 + .equ s5,0xffff00 + .equ s6,0xffff7fff + .equ s7,0xffff8000 + .equ s8,0xfffffeff + .equ s9,0xffffff00 + .equ s10,0xffffffff + .end