From: Andrew Stubbs <ams@codesourcery.com>
Date: Fri, 24 May 2019 11:06:18 +0000 (+0000)
Subject: Fix 64-bit addition in prologue.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3258c2d6fb886798b320b33b832ee5747f7c0de8;p=gcc.git

Fix 64-bit addition in prologue.

2019-05-24  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn.c (gcn_expand_prologue): Use gen_addsi3_scalar_carry
	for lo-part.

From-SVN: r271600
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index daaa8c8f7c5..9c7cd73cd8b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-05-24  Andrew Stubbs  <ams@codesourcery.com>
+
+	* config/gcn/gcn.c (gcn_expand_prologue): Use gen_addsi3_scalar_carry
+	for lo-part.
+
 2019-05-24  Matthew Malcomson  <matthew.malcomson@arm.com>
 
 	PR target/90588
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 47630c6edb4..71f4b4ce35a 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -2824,9 +2824,9 @@ gcn_expand_prologue ()
       emit_move_insn (fp_lo, gen_rtx_REG (SImode, 0));
       emit_insn (gen_andsi3_scc (fp_hi, gen_rtx_REG (SImode, 1),
 				 gen_int_mode (0xffff, SImode)));
-      emit_insn (gen_addsi3_scc (fp_lo, fp_lo, wave_offset));
-      emit_insn (gen_addcsi3_scalar_zero (fp_hi, fp_hi,
-					  gen_rtx_REG (BImode, SCC_REG)));
+      rtx scc = gen_rtx_REG (BImode, SCC_REG);
+      emit_insn (gen_addsi3_scalar_carry (fp_lo, fp_lo, wave_offset, scc));
+      emit_insn (gen_addcsi3_scalar_zero (fp_hi, fp_hi, scc));
 
       if (sp_adjust > 0)
 	emit_insn (gen_adddi3_scc (sp, fp, gen_int_mode (sp_adjust, DImode)));