From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 27 May 2020 15:19:31 +0000 (+0100)
Subject: add carry-out, overflow and cr0 ok setting in ALU main_stage
X-Git-Tag: div_pipeline~791
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32602780575dedfd322945760769201f0565cfe2;p=soc.git

add carry-out, overflow and cr0 ok setting in ALU main_stage
---

diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index ec892a13..b39d0199 100644
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -69,8 +69,10 @@ class ALUMainStage(PipeModBase):
                 # https://bugs.libre-soc.org/show_bug.cgi?id=319#c5
                 comb += cry_o.data[0].eq(add_o[-1]) # XER.CO
                 comb += cry_o.data[1].eq(add_o[33] ^ (a[32] ^ b[32])) # XER.CO32
+                comb += cry_o.ok.eq(1)
                 comb += ov_o.data[0].eq((add_o[-2] != a[-1]) & (a[-1] == b[-1]))
                 comb += ov_o.data[1].eq((add_o[32] != a[31]) & (a[31] == b[31]))
+                comb += ov_o.ok.eq(1)
 
             #### exts (sign-extend) ####
             with m.Case(InternalOp.OP_EXTS):
@@ -89,6 +91,7 @@ class ALUMainStage(PipeModBase):
                 for i in range(8):
                     comb += eqs[i].eq(src1 == b[8*i:8*(i+1)])
                 comb += cr0.data.eq(Cat(Const(0, 2), eqs.any(), Const(0, 1)))
+                comb += cr0.ok.eq(1)
 
             with m.Default():
                 comb += o.ok.eq(0)