From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 23 Feb 2011 21:10:49 +0000 (-0600)
Subject: ARM: Squash state on FPSCR stride or len write.
X-Git-Tag: stable_2012_02_02~536
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=326191adc9ed16c672a7f2442055dc8a23626739;p=gem5.git

ARM: Squash state on FPSCR stride or len write.
---

diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 961b9a355..4911d50f1 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -209,7 +209,8 @@ let {{
                                  { "code": vmsrFpscrCode,
                                    "predicate_test": predicateTest,
                                    "op_class": "SimdFloatMiscOp" },
-                                 ["IsSerializeAfter","IsNonSpeculative"])
+                                 ["IsSerializeAfter","IsNonSpeculative",
+                                  "IsSquashAfter"])
     header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
     decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
     exec_output += PredOpExecute.subst(vmsrFpscrIop);