From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 13 Mar 2015 22:19:08 +0000 (+0100)
Subject: soc/sdram: sync with new mibuild toolchain management
X-Git-Tag: 24jan2021_ls180~2490
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32676fffd22b7b1c3cfaf7ed2baff1baa9200c51;p=litex.git

soc/sdram: sync with new mibuild toolchain management
---

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index e9fbca15..e6ecb930 100644
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -53,8 +53,8 @@ class SDRAMSoC(SoC):
 				# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
 				# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
 				# Remove this workaround when fixed by Xilinx.
-				from mibuild.xilinx.vivado import XilinxVivadoPlatform
-				if isinstance(self.platform, XilinxVivadoPlatform):
+				from mibuild.xilinx.vivado import XilinxVivadoToolchain
+				if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
 					from migen.fhdl.simplify import FullMemoryWE
 					self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master()))
 				else: