From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Apr 2020 12:14:37 +0000 (+0100)
Subject: whoops missed modulo
X-Git-Tag: convert-csv-opcode-to-binary~2940
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3288026204ff16d268f0040288077020a07bebd0;p=libreriscv.git

whoops missed modulo
---

diff --git a/openpower/isa/stringldst.mdwn b/openpower/isa/stringldst.mdwn
index 4ded1cd3a..c1f906947 100644
--- a/openpower/isa/stringldst.mdwn
+++ b/openpower/isa/stringldst.mdwn
@@ -11,7 +11,7 @@ X-Form
     i <- 32
     do while n > 0
         if i = 32 then
-            r <- r + 1 (mod 32)
+            r <- (r + 1) % 32
             GPR(r) <- 0
         GPR(r)[i:i+7] <- MEM(EA, 1)
         i <- i + 8