From: lkcl <lkcl@web>
Date: Mon, 23 May 2022 14:59:51 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2137
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=328cff066621e28c901c331ed5f140a1ab22c407;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 5a054070f..0da7909c2 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -57,10 +57,7 @@ The pseudocode for `madded RT, RA, RB, RC` is:
     RT <- sum[64:127]
     RS <- sum[0:63] # RS implicit register, see below
 
-* In Scalar (non-SVP64) usage: `RS=RT+1`
-* For SVP64: RS may be either RC or RT+MAXVL
-
-RC is zero-extended (not shifted), the 128-bit product added
+RC is zero-extended (not shifted, not sign-extended), the 128-bit product added
 to it; the lower half of that result stored in RT and the upper half
 in RS.
 
@@ -118,7 +115,13 @@ RB, the divisor, remains 64 bit.  The instruction is therefore a 128/64
 division, producing a (pair) of 64 bit result(s).  Overflow conditions
 are detected in exactly the same fashion as `divdeu`, except that rather
 than have `UNDEFINED` behaviour, RT is set to all ones and RS set to all
-zeros.
+zeros on overflow.
+
+*Programmer's note: there are no Rc variants of any of these VA-Form
+instructions. `cmpi` will need to be used to detect overflow conditions:
+the saving in instruction count is that both RT and RS will have already
+been set to useful values needed as part of implementing Knuth's
+Algorithm D*
 
 For SVP64, given that this instruction is also 3-in 2-out 64-bit registers,
 the exact same EXTRA format and setting of RS is used as for `sv.madded`.
@@ -133,13 +136,10 @@ Pseudo-code:
         modulo <- dividend % divisor
         RT <- result[XLEN:(XLEN*2)-1]
         RS <- modulo[XLEN:(XLEN*2)-1]
-        overflow <- 0
     else
-        overflow <- 1
         RT <- [1]*XLEN
         RS <- [0]*XLEN
 
-
 # [DRAFT] EXT04 Proposed Map
 
 For the Opcode map (XO Field)