From: Luke Kenneth Casson Leighton Date: Tue, 4 Aug 2020 09:41:45 +0000 (+0100) Subject: more remove wildcard imports X-Git-Tag: semi_working_ecp5~457 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=328f0a41c3faa113c31b6d1301e149f8e5da35b6;p=soc.git more remove wildcard imports --- diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index 4c4154d6..3d4d7a39 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -1,6 +1,6 @@ import os -from migen import * +from migen import ClockSignal, ResetSignal, Signal, Instance, Cat from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU diff --git a/src/soc/litex/florent/microwatt/core.py b/src/soc/litex/florent/microwatt/core.py index b57f7bcf..704eb18f 100644 --- a/src/soc/litex/florent/microwatt/core.py +++ b/src/soc/litex/florent/microwatt/core.py @@ -4,7 +4,7 @@ import os -from migen import * +from migen import ClockSignal, ResetSignal, Signal, Instance, Cat from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -48,8 +48,8 @@ class Microwatt(CPU): self.platform = platform self.variant = variant self.reset = Signal() - self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29) - self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29) + self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29) + self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29) self.periph_buses = [ibus, dbus] self.memory_buses = [] diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index a24833d8..09674ae6 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -3,7 +3,7 @@ import os import argparse -from migen import Signal, FSM +from migen import Signal, FSM, If, Display, Finish from litex.build.generic_platform import Pins, Subsignal from litex.build.sim import SimPlatform