From: Ron Dreslinski <rdreslin@umich.edu>
Date: Thu, 6 Jul 2006 19:15:37 +0000 (-0400)
Subject: Now timing reads work in single level of cache with simple cpu
X-Git-Tag: m5_2.0_beta1~36^2~18^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=329e32f8c63a5982b29c2d620e7d08708ec62fbd;p=gem5.git

Now timing reads work in single level of cache with simple cpu

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
    Changes to handle timing reads in Simple CPU (blocking buffers)

--HG--
extra : convert_revision : a2e7d4287d7cdfd1bbf9c929ecbeafde499a5b9f
---

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index aaaf1bdef..15a21efa1 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -98,6 +98,37 @@ BaseCache::CachePort::clearBlocked()
     blocked = false;
 }
 
+BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
+    : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
+{
+    this->setFlags(AutoDelete);
+    pkt = NULL;
+}
+
+BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
+    : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
+{
+    this->setFlags(AutoDelete);
+}
+
+void
+BaseCache::CacheEvent::process()
+{
+    if (!pkt)
+    {
+        if (!cachePort->isCpuSide)
+            pkt = cachePort->cache->getPacket();
+        //Else get coherence req
+    }
+    cachePort->sendTiming(pkt);
+}
+
+const char *
+BaseCache::CacheEvent::description()
+{
+    return "timing event\n";
+}
+
 Port*
 BaseCache::getPort(const std::string &if_name, int idx)
 {
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 2754fab5a..5370a73c8 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -79,9 +79,9 @@ class BaseCache : public MemObject
 {
     class CachePort : public Port
     {
+      public:
         BaseCache *cache;
 
-      public:
         CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
 
       protected:
@@ -110,10 +110,11 @@ class BaseCache : public MemObject
 
     struct CacheEvent : public Event
     {
-        Packet *pkt;
         CachePort *cachePort;
+        Packet *pkt;
 
-        CacheEvent(Packet *pkt, CachePort *cachePort);
+        CacheEvent(CachePort *_cachePort);
+        CacheEvent(CachePort *_cachePort, Packet *_pkt);
         void process();
         const char *description();
     };
@@ -147,6 +148,11 @@ class BaseCache : public MemObject
         fatal("No implementation");
     }
 
+    virtual Packet *getPacket()
+    {
+        fatal("No implementation");
+    }
+
     /**
      * Bit vector of the blocking reasons for the access path.
      * @sa #BlockedCause
@@ -388,7 +394,6 @@ class BaseCache : public MemObject
         if (!isBlockedForSnoop()) {
            memSidePort->clearBlocked();
         }
-
     }
 
     /**
@@ -407,10 +412,13 @@ class BaseCache : public MemObject
      */
     void setMasterRequest(RequestCause cause, Tick time)
     {
+        if (!doMasterRequest())
+        {
+            BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
+            reqCpu->schedule(time);
+        }
         uint8_t flag = 1<<cause;
         masterRequests |= flag;
-        assert("Implement\n" && 0);
-//	mi->pktuest(time);
     }
 
     /**
@@ -462,8 +470,10 @@ class BaseCache : public MemObject
      */
     void respond(Packet *pkt, Tick time)
     {
-        assert("Implement\n" && 0);
-//	si->respond(pkt,time);
+        pkt->makeTimingResponse();
+        pkt->result = Packet::Success;
+        CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
+        reqCpu->schedule(time);
     }
 
     /**
@@ -476,8 +486,10 @@ class BaseCache : public MemObject
         if (!pkt->req->isUncacheable()) {
             missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time;
         }
-        assert("Implement\n" && 0);
-//	si->respond(pkt,time);
+        pkt->makeTimingResponse();
+        pkt->result = Packet::Success;
+        CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
+        reqCpu->schedule(time);
     }
 
     /**
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 1243c9d9e..2e77444a0 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -168,7 +168,7 @@ class Cache : public BaseCache
      * Selects a request to send on the bus.
      * @return The memory request to service.
      */
-    Packet * getPacket();
+    virtual Packet * getPacket();
 
     /**
      * Was the request was sent successfully?
@@ -241,17 +241,6 @@ class Cache : public BaseCache
         return missQueue->getMisses();
     }
 
-    /**
-     * Send a response to the slave interface.
-     * @param req The request being responded to.
-     * @param time The time the response is ready.
-     */
-    void respond(Packet * &pkt, Tick time)
-    {
-        //si->respond(pkt,time);
-        cpuSidePort->sendAtomic(pkt);
-    }
-
     /**
      * Perform the access specified in the request and return the estimated
      * time of completion. This function can either update the hierarchy state