From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 23 Sep 2021 13:59:52 +0000 (+0100)
Subject: add fsubs unit test
X-Git-Tag: sv_maxu_works-initial~845
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32a18d1d8220923ee84d1b2c1b78b651c33e9715;p=openpower-isa.git

add fsubs unit test
---

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index 615ff5d5..6dc4fd90 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -176,6 +176,23 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
             self.assertEqual(sim.fpr(3), SelectableInt(0, 64))
 
+    def test_fp_subs(self):
+        """>>> lst = ["fsubs 3, 1, 2",
+                     ]
+        """
+        lst = ["fsubs 3, 1, 2", # 0 - -32.3 = 32.3
+                     ]
+
+        fprs = [0] * 32
+        fprs[1] = 0x0
+        fprs[2] = 0xC040266660000000
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            self.assertEqual(sim.fpr(1), SelectableInt(0x0, 64))
+            self.assertEqual(sim.fpr(2), SelectableInt(0xC040266660000000, 64))
+            self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64))
+
     def test_fp_add(self):
         """>>> lst = ["fadd 3, 1, 2",
                      ]