From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 12 Feb 2019 13:09:18 +0000 (+0000)
Subject: arch-arm: Trap virtual accesses to GICv3 SGI registers
X-Git-Tag: v19.0.0.0~818
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32a23114c14cebc5ec0067ac739144b50e412219;p=gem5.git

arch-arm: Trap virtual accesses to GICv3 SGI registers

According to GICv3 documentation, a virtual write (which means
HCR.IMO/FMO = 1) to ICC_SGI0R_EL1, ICC_SGI1R_EL1, ICC_ASGI1R_EL1 should
trap to EL2.

Change-Id: Ie7a952c2ff08590bb0c6e3854df567d714c2dc94
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17990
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index c219bd9ad..fed2d9ac8 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013,2017-2018 ARM Limited
+ * Copyright (c) 2011-2013,2017-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -38,6 +38,7 @@
  */
 
 #include "arch/arm/insts/misc64.hh"
+#include "arch/arm/isa.hh"
 
 std::string
 ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
@@ -268,6 +269,16 @@ MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
             break;
           case MISCREG_IMPDEF_UNIMPL:
             trap_to_hyp = hcr.tidcp && el == EL1;
+          // GICv3 regs
+          case MISCREG_ICC_SGI0R_EL1:
+            if (tc->getIsaPtr()->haveGICv3CpuIfc())
+                trap_to_hyp = hcr.fmo && el == EL1;
+            break;
+          case MISCREG_ICC_SGI1R_EL1:
+          case MISCREG_ICC_ASGI1R_EL1:
+            if (tc->getIsaPtr()->haveGICv3CpuIfc())
+                trap_to_hyp = hcr.imo && el == EL1;
+            break;
           default:
             break;
         }
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index b41134f03..2888ebbf3 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2014, 2016-2018 ARM Limited
+ * Copyright (c) 2009-2014, 2016-2019 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -580,6 +580,16 @@ mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss)
               case MISCREG_PMCR:
                 trapToHype = hdcr.tpmcr;
                 break;
+              // GICv3 regs
+              case MISCREG_ICC_SGI0R:
+                if (tc->getIsaPtr()->haveGICv3CpuIfc())
+                    trapToHype = hcr.fmo;
+                break;
+              case MISCREG_ICC_SGI1R:
+              case MISCREG_ICC_ASGI1R:
+                if (tc->getIsaPtr()->haveGICv3CpuIfc())
+                    trapToHype = hcr.imo;
+                break;
               // No default action needed
               default:
                 break;