From: Daniel Vetter Date: Wed, 9 Oct 2013 13:49:11 +0000 (+0200) Subject: i965: CS writes/reads should use I915_GEM_INSTRUCTION X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32a3f5f6d768e5828be1d1f46b1b3f819f55cba8;p=mesa.git i965: CS writes/reads should use I915_GEM_INSTRUCTION Otherwise the gen6 w/a in the kernel won't kick in and the write will land nowhere. Inspired by a patch Ken pointed me at which had the same issue (but isn't yet merged and also for a gen7+ feature). An audit of the entire driver didn't reveal any other case than the one in in the write_reg helper used by the gen6 queryobj code. Acked-by: Kenneth Graunke Signed-off-by: Daniel Vetter Tested-by: Xinkai Chen Reviewed-by: Eric Anholt Cc: "9.2" --- diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c index add4df94ea3..56e9d5db937 100644 --- a/src/mesa/drivers/dri/i965/gen6_queryobj.c +++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c @@ -115,14 +115,14 @@ brw_store_register_mem64(struct brw_context *brw, BEGIN_BATCH(3); OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); OUT_BATCH(reg); - OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, idx * sizeof(uint64_t)); ADVANCE_BATCH(); BEGIN_BATCH(3); OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); OUT_BATCH(reg + sizeof(uint32_t)); - OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, sizeof(uint32_t) + idx * sizeof(uint64_t)); ADVANCE_BATCH(); }