From: lkcl Date: Tue, 4 Oct 2022 13:21:44 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~184 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32a84b3e739a0e057470b897cb78524c1697f0ca;p=libreriscv.git --- diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn index 6a27fc65d..51e56d3f3 100644 --- a/openpower/sv/svp64/discussion.mdwn +++ b/openpower/sv/svp64/discussion.mdwn @@ -97,7 +97,6 @@ Some examples on different operation widths: 256 + 2 = 2 # this is correct whether we use the larger or smaller width # aka hw can optimize narrowing addition - # Notes about Swizzle Basically, there isn't enough room to try to fit two src src1/2 swizzle, and SV, even into 64 bit (actually 24) without severely compromising on the number of bits allocated to either swizzle, or SV, or both. @@ -128,7 +127,7 @@ all of which screams, "this is going in completely the wrong direction". keep i # note about INT predicate -001 ALWAYS (implicit) Operation is not masked + 001 ALWAYS (implicit) Operation is not masked this means by default that 001 will always be in nonpredicated ops, which seems anomalous. would 000 be better to indicate "no predication"? @@ -338,7 +337,9 @@ and failfirst needs to be an Illegal Instruction. [[sv/branches]] is so heavily interdependent in CTR-test and VLSet Modes, and only having a single source (BI) that it is simply strongly -recommended not to interfere with its behaviour, at all. +recommended not to interfere with its behaviour, at all. additionally +the unaltered behaviour is needed to substitute for the loss of +all-ones predicate mask behaviour on SV-scalar-regs ## answers to 4, loops/uses @@ -373,7 +374,8 @@ a need for merging (ORing) all bits into a single alternative predicate mask A major motivation for changing SVP64 with all isvec=0 to temporarily override VL to 1 is to allow supporting traditional SIMD that has constantly varying element sizes (and therefore vector lengths too) -without needing setvl every few instructions. +without needing setvl every few instructions, by using SUBVL and +elwidth overrides. Examples of use cases: