From: whitequark <cz@m-labs.hk>
Date: Tue, 22 Jan 2019 17:51:44 +0000 (+0000)
Subject: back.pysim: fix behavior of initial cycle for sync processes.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32aa7a2fec98631e2bab5790b5cb3296b0f10913;p=nmigen.git

back.pysim: fix behavior of initial cycle for sync processes.

The current behavior was introduced in 65702719, which was a wrong
fix for an issue that was actually fixed in 12e04e4e. This commit
effectively reverts 65702719 and 1782b841.
---

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index a19905d..21885a8 100644
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -414,13 +414,13 @@ class Simulator:
         process = self._check_process(process)
         def sync_process():
             try:
-                result = None
+                cmd = None
                 while True:
-                    self._process_loc[sync_process] = self._name_process(process)
-                    cmd = process.send(result)
                     if cmd is None:
                         cmd = Tick(domain)
                     result = yield cmd
+                    self._process_loc[sync_process] = self._name_process(process)
+                    cmd = process.send(result)
             except StopIteration:
                 pass
         sync_process = sync_process()
diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py
index 6e8e679..e26d3d4 100644
--- a/nmigen/lib/fifo.py
+++ b/nmigen/lib/fifo.py
@@ -72,9 +72,9 @@ class FIFOInterface:
 
     def read(self):
         """Read method for simulation."""
+        assert (yield self.readable)
         yield self.re.eq(1)
         yield
-        assert (yield self.readable)
         value = (yield self.dout)
         yield self.re.eq(0)
         return value
diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py
index d1f769e..20f6fa1 100644
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@@ -279,9 +279,6 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
         with self.assertSimulation(self.m) as sim:
             sim.add_clock(1e-6, domain="sync")
             def process():
-                self.assertEqual((yield self.count), 4)
-                self.assertEqual((yield self.sync.clk), 0)
-                yield
                 self.assertEqual((yield self.count), 4)
                 self.assertEqual((yield self.sync.clk), 1)
                 yield