From: Adrian Herrera Date: Fri, 2 Oct 2020 07:48:23 +0000 (+0100) Subject: configs: MemConfig, add QoSMemSinkCtrl support X-Git-Tag: develop-gem5-snapshot~273 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32b3be789de6bebc8db2682c17334d48e5398eb4;p=gem5.git configs: MemConfig, add QoSMemSinkCtrl support QoSMemSinkInterface is a special case of memory interface type, similar to SimpleMemory. It requires a QoSMemSinkCtrl where most model parameters are exposed. By adding support in "config_mem", we allow configurations with multiple QoSMemSinkCtrls to be centrally configured, particularly interleaving parameters. Change-Id: I46462b55d587acd2c861963bc0279bce92d5f450 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35797 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index 8221f85f0..63301abca 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -229,11 +229,15 @@ def config_mem(options, system): static_frontend_latency = '4ns') elif opt_mem_type == "SimpleMemory": mem_ctrl = m5.objects.SimpleMemory() + elif opt_mem_type == "QoSMemSinkInterface": + mem_ctrl = m5.objects.QoSMemSinkCtrl() else: mem_ctrl = m5.objects.MemCtrl() # Hookup the controller to the interface and add to the list - if opt_mem_type != "SimpleMemory": + if opt_mem_type == "QoSMemSinkInterface": + mem_ctrl.interface = dram_intf + elif opt_mem_type != "SimpleMemory": mem_ctrl.dram = dram_intf mem_ctrls.append(mem_ctrl)