From: Nick Clifton Date: Tue, 12 May 1998 20:38:36 +0000 (+0000) Subject: Add --enable-special command line switch. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32c2be763313cea5e3bf448f2de2bf29be09d5c9;p=binutils-gdb.git Add --enable-special command line switch. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 1a84acf36b9..f3203de3d9d 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +start-sanitize-m32rx +Tue May 12 13:34:12 1998 Nick Clifton + + * config/tc-m32r.c: Add command line switch to support special + M32Rx instructions. + * doc/c-m32r.texi: Document new command line switch. + +end-sanitize-m32rx Tue May 12 12:03:44 1998 Richard Henderson * config/tc-d30v.c (cur_mul32_p, prev_mul32_p): Make static. diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c index 31c491587d3..ff885c004af 100644 --- a/gas/config/tc-m32r.c +++ b/gas/config/tc-m32r.c @@ -75,10 +75,14 @@ static int m32r_relax; static char * m32r_cpu_desc; /* start-sanitize-m32rx */ -/* Non-zero if -m32rx has been specified, in which case support for the +/* Non-zero if --m32rx has been specified, in which case support for the extended M32RX instruction set should be enabled. */ static int enable_m32rx = 0; +/* Non-zero if --enable-special has been specified, in which case support for + the special M32RX instruction set should be enabled. */ +static int enable_special = 0; + /* Non-zero if the programmer should be warned when an explicit parallel instruction might have constraint violations. */ static int warn_explicit_parallel_conflicts = 1; @@ -153,12 +157,14 @@ struct option md_longopts[] = #define OPTION_NO_WARN (OPTION_MD_BASE + 2) {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN}, {"Wnp", no_argument, NULL, OPTION_NO_WARN}, +#define OPTION_SPECIAL (OPTION_MD_BASE + 3) + {"enable-special", no_argument, NULL, OPTION_SPECIAL}, /* end-sanitize-m32rx */ #if 0 /* not supported yet */ -#define OPTION_RELAX (OPTION_MD_BASE + 3) +#define OPTION_RELAX (OPTION_MD_BASE + 4) {"relax", no_argument, NULL, OPTION_RELAX}, -#define OPTION_CPU_DESC (OPTION_MD_BASE + 4) +#define OPTION_CPU_DESC (OPTION_MD_BASE + 5) {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, #endif @@ -189,6 +195,11 @@ md_parse_option (c, arg) case OPTION_NO_WARN: warn_explicit_parallel_conflicts = 0; break; + + case OPTION_SPECIAL: + allow_m32rx (1); + enable_special = 1; + break; /* end-sanitize-m32rx */ #if 0 /* not supported yet */ @@ -213,6 +224,8 @@ md_show_usage (stream) fprintf (stream, _("M32R/X specific command line options:\n")); fprintf (stream, _("\ --m32rx support the extended m32rx instruction set\n")); + fprintf (stream, _("\ +--enable-special support the special m32rx instructions\n")); fprintf (stream, _("\ -O try to combine instructions in parallel\n")); @@ -701,14 +714,24 @@ assemble_parallel_insn (str, str2) return; } - if (! enable_m32rx + if (! enable_special + && CGEN_INSN_ATTR (first.insn, CGEN_INSN_SPECIAL)) + { + /* xgettext:c-format */ + as_bad (_("unknown instruction '%s'"), str); + + return; + } + else if (! enable_m32rx /* FIXME: Need standard macro to perform this test. */ && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) { + /* xgettext:c-format */ as_bad (_("instruction '%s' is for the M32RX only"), str); + return; } - + /* Check to see if this is an allowable parallel insn. */ if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) { @@ -752,9 +775,18 @@ assemble_parallel_insn (str, str2) } /* Check it. */ - if (! enable_m32rx + if (! enable_special + && CGEN_INSN_ATTR (second.insn, CGEN_INSN_SPECIAL)) + { + /* xgettext:c-format */ + as_bad (_("unknown instruction '%s'"), str); + + return; + } + else if (! enable_m32rx && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) { + /* xgettext:c-format */ as_bad (_("instruction '%s' is for the M32RX only"), str); return; } @@ -771,6 +803,7 @@ assemble_parallel_insn (str, str2) if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) { + /* xgettext:c-format */ as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); return; } @@ -796,9 +829,11 @@ assemble_parallel_insn (str, str2) if (warn_explicit_parallel_conflicts) { if (first_writes_to_seconds_operands (& first, & second, false)) + /* xgettext:c-format */ as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); if (first_writes_to_seconds_operands (& second, & first, false)) + /* xgettext:c-format */ as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); } @@ -887,8 +922,18 @@ md_assemble (str) } /* start-sanitize-m32rx */ - if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) + if (! enable_special + && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_SPECIAL)) + { + /* xgettext:c-format */ + as_bad (_("unknown instruction '%s'"), str); + + return; + } + else if (! enable_m32rx + && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) { + /* xgettext:c-format */ as_bad (_("instruction '%s' is for the M32RX only"), str); return; } diff --git a/gas/doc/c-m32r.texi b/gas/doc/c-m32r.texi index df36aaa6623..cc834d6cdf0 100644 --- a/gas/doc/c-m32r.texi +++ b/gas/doc/c-m32r.texi @@ -40,6 +40,13 @@ to the M32RX microprocessor, which adds some more instructions to the basic M32R instruction set, and some additional parameters to some of the original instructions. +@item --enable-special +@cindex @samp{--enable-special} option, M32RX +@cindex architecture options, M32RX +@cindex M32R architecture options +This option is the equivalent of the @emph{--m32rx} option, except that +it also allows the special M32RX instructions to be assembled as well. + @item --warn-explicit-parallel-conflicts @cindex @samp{--warn-explicit-parallel-conflicts} option, M32RX Instructs @code{@value{AS}} to produce warning messages when @@ -52,11 +59,21 @@ different result from @samp{mv r1, r2 \n mv r3, r1} since the former moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 and r3. +@item --Wp +@cindex @samp{--Wp} option, M32RX +This is a shorter synonym for the @emph{--warn-explicit-parallel-conflicts} +option. + @item --no-warn-explicit-parallel-conflicts @cindex @samp{--no-warn-explicit-parallel-conflicts} option, M32RX Instructs @code{@value{AS}} not to produce warning messages when questionable parallel instructions are encountered. +@item --Wnp +@cindex @samp{--Wnp} option, M32RX +This is a shorter synonym for the @emph{--no-warn-explicit-parallel-conflicts} +option. + @end table @node M32R-Warnings @@ -94,6 +111,10 @@ which is only supported by the M32Rx processor, and the @samp{--m32rx} command line flag has not been specified to allow assembly of such instructions. +@item unknown instruction @samp{...} +This message is produced when the assembler encounters an instruction +which it doe snot recognise. + @item only the NOP instruction can be issued in parallel on the m32r This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the @@ -117,6 +138,7 @@ For example these code fragments will produce this message: @samp{jl r0 || mv r14, r1} @samp{st r2, @@-r1 || mv r1, r3} @samp{mv r1, r2 || ld r0, @@r1+} +@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit) @end table @c end-sanitize-m32rx