From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 Aug 2020 22:27:02 +0000 (+0100)
Subject: argh, reading regfile over DMI was overlapped and corrupting reg 0
X-Git-Tag: semi_working_ecp5~262
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32d2d85a5af1f3cef1d5c0d7ea11036b6e675829;p=soc.git

argh, reading regfile over DMI was overlapped and corrupting reg 0
---

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index e4a1fbbf..688fde4b 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -285,7 +285,7 @@ class LibreSoCSim(SoCSDRAM):
 
         # read all 32 GPRs
         for i in range(32):
-            self.sync += If(active_dbg & (dmicount == 14+(i*8)),
+            self.sync += If(active_dbg & (dmicount == 16+(i*8)),
                 (dmi_addr.eq(0b100), # GSPR addr
                  dmi_din.eq(i), # r1
                  dmi_req.eq(1),
@@ -293,7 +293,7 @@ class LibreSoCSim(SoCSDRAM):
                 )
             )
 
-            self.sync += If(active_dbg & (dmicount == 18+(i*8)),
+            self.sync += If(active_dbg & (dmicount == 20+(i*8)),
                 (dmi_addr.eq(0b101), # GSPR data
                  dmi_req.eq(1),
                  dmi_wen.eq(0),