From: Sean Cross <sean@xobs.io>
Date: Thu, 5 Jul 2018 08:56:13 +0000 (+0800)
Subject: soc_core: uart: add a reset line to the UART
X-Git-Tag: 24jan2021_ls180~1685^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32d5a751db2395b2d26ac4334b63212d7154c24b;p=litex.git

soc_core: uart: add a reset line to the UART

Enable resetting the UART by adding a ResetInserter to the UART.

The UART must be reset when resetting the softcore.

Signed-off-by: Sean Cross <sean@xobs.io>
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 50feab0b..5af8f55f 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -148,7 +148,8 @@ class SoCCore(Module):
                 self.submodules.uart  = uart.UARTStub()
             else:
                 self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
-                self.submodules.uart = uart.UART(self.uart_phy)
+                self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
+
         #else:
         #    del self.soc_interrupt_map["uart"]