From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 19 Jun 2020 02:06:41 +0000 (+0100)
Subject: do mix-in for test_sim.py so that jacob can write some div tests without
X-Git-Tag: div_pipeline~323
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32db050bdcccd20dbe1437d6f81d74f3ff2c9ceb;p=soc.git

do mix-in for test_sim.py so that jacob can write some div tests without
having to run all the other ones
---

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 9ab807d6..de4193bc 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -207,7 +207,7 @@ class GeneralTestCases(FHDLTestCase):
         self.test_data.append(tc)
 
 
-class DecoderTestCase(GeneralTestCases):
+class DecoderBase:
 
     def run_tst(self, generator, initial_mem=None):
         m = Module()
@@ -290,5 +290,9 @@ class DecoderTestCase(GeneralTestCases):
             self.assertEqual(qemu_val, sim_val)
 
 
+class DecoderTestCase(DecoderBase, GeneralTestCases):
+    pass
+
+
 if __name__ == "__main__":
     unittest.main()