From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 7 Apr 2013 14:42:29 +0000 (+0200)
Subject: Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v
X-Git-Tag: yosys-0.2.0~652
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32dbf7752d5ae41966bf19773bf8561b538fe8f0;p=yosys.git

Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v
---

diff --git a/techlibs/simlib.v b/techlibs/simlib.v
index 8675a4d0f..ff988cbe5 100644
--- a/techlibs/simlib.v
+++ b/techlibs/simlib.v
@@ -799,8 +799,8 @@ parameter MEMID = "";
 parameter ABITS = 8;
 parameter WIDTH = 8;
 
-parameter RD_CLK_ENABLE = 0;
-parameter RD_CLK_POLARITY = 0;
+parameter CLK_ENABLE = 0;
+parameter CLK_POLARITY = 0;
 
 input CLK;
 input [ABITS-1:0] ADDR;
@@ -821,8 +821,8 @@ parameter MEMID = "";
 parameter ABITS = 8;
 parameter WIDTH = 8;
 
-parameter RD_CLK_ENABLE = 0;
-parameter RD_CLK_POLARITY = 0;
+parameter CLK_ENABLE = 0;
+parameter CLK_POLARITY = 0;
 
 input CLK, EN;
 input [ABITS-1:0] ADDR;