From: lkcl <lkcl@web>
Date: Fri, 25 Dec 2020 00:20:14 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~933
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32edb2b385a6d09330d9c12124db69fa2ae0286d;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index a5f4fec12..8901189be 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -15,7 +15,8 @@ The fundamentals are:
 
 * The Program Counter gains a "Sub Counter" context.
 * Vectorisation pauses the PC and runs a loop from 0 to VL-1
- (where VL is Vector Length)
+ (where VL is Vector Length). This may be thought of as a
+   "Sub-PC"
 * Some registers may be "tagged" as Vectors
 * During the loop, "Vector"-tagged register are incremented by
   one with each iteration, executing the *same instruction*