From: lkcl Date: Sun, 9 Oct 2022 21:51:59 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~117 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=32ef25463f7ef08346b07dba50b6866e2d60666f;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls002/discussion.mdwn b/openpower/sv/rfc/ls002/discussion.mdwn index b95d8cef9..3851b0862 100644 --- a/openpower/sv/rfc/ls002/discussion.mdwn +++ b/openpower/sv/rfc/ls002/discussion.mdwn @@ -187,7 +187,16 @@ ack. TODO. it is unlikely that we (Libre-SOC) will initially implement any of v3.1 64-bit prefixing (it cannot be Vectorised, resulting unacceptably in 96-bit instructions which we decided is too much). that said, the LD -addressing immediate extended range is extremely useful (along with the PC-relative modes and also other instructions such as paddi). +addressing immediate extended range is extremely useful +(along with the PC-relative modes and also other instructions +such as paddi). bottom line we have not yet given much thought to using any v3.1 Scalar Prefixed instructions, at all, so don't even know most of what they do. + +that said: if `paddi` puts 32-bits into a GPR, and does so in 64 bits, +is it not similarly redundant i.e. exactly the same amount of space +used as two 32-bit instructions? if `paddi` puts *more* than 32 bits +into a GPR then it is not the same and would not make a comparative +analogy as a Programmer's Note. +