From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 22 Dec 2022 13:04:51 +0000 (+0000)
Subject: mention SVP64 in ls005
X-Git-Tag: opf_rfc_ls005_v1~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3309a6a452b6ccc5f90eb1c7771a098fc8343763;p=libreriscv.git

mention SVP64 in ls005
---

diff --git a/openpower/sv/rfc/ls005.mdwn b/openpower/sv/rfc/ls005.mdwn
index a66b4234e..22888b94c 100644
--- a/openpower/sv/rfc/ls005.mdwn
+++ b/openpower/sv/rfc/ls005.mdwn
@@ -85,6 +85,11 @@ this with the more "normal" approach of creating heavily-focussed
 specialist "AI" Engines incapable of Turing-completeness and the benefits
 are clear.
 
+Note: SVP64 **requires** this change as a 100% critical dependency.
+SIMD back-end ALUs process Vectors of "Elements" at 8, 16 and 32-bit (and
+64-bit), read from, processed, and returned to, the standard **Scalar**
+Register Files, with byte-level write-enable lines.
+
 **Changes**
 
 For all pseudocode right across the board in all Scalar operations, replace