From: Paul Berry <stereotype441@gmail.com>
Date: Fri, 6 Jul 2012 01:50:56 +0000 (-0700)
Subject: i965/msaa: Enable CMS layout on Gen7 for the formats that support it.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33202b4876a88b6f54ca7022eadd2875a2d3508a;p=mesa.git

i965/msaa: Enable CMS layout on Gen7 for the formats that support it.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
---

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 358431b2081..4e892b27fd1 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -293,7 +293,24 @@ compute_msaa_layout(struct intel_context *intel, gl_format format)
    case GL_DEPTH_STENCIL:
       return INTEL_MSAA_LAYOUT_IMS;
    default:
-      return INTEL_MSAA_LAYOUT_UMS;
+      /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
+       *
+       *   This field must be set to 0 for all SINT MSRTs when all RT channels
+       *   are not written
+       *
+       * In practice this means that we have to disable MCS for all signed
+       * integer MSAA buffers.  The alternative, to disable MCS only when one
+       * of the render target channels is disabled, is impractical because it
+       * would require converting between CMS and UMS MSAA layouts on the fly,
+       * which is expensive.
+       */
+      if (_mesa_get_format_datatype(format) == GL_INT) {
+         /* TODO: is this workaround needed for future chipsets? */
+         assert(intel->gen == 7);
+         return INTEL_MSAA_LAYOUT_UMS;
+      } else {
+         return INTEL_MSAA_LAYOUT_CMS;
+      }
    }
 }