From: lkcl Date: Sun, 12 Sep 2021 10:19:53 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~149 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3326e330f10150133ce99b4430037e8ea1a2da90;p=libreriscv.git --- diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 2dd1976d6..bed5834f1 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -115,6 +115,11 @@ instructions are still *completely separate and independent*, being unaltered and unaffected by their SVP64 variants in every conceivable way. +*Programming note: One important point is that SVP64 instructions are 64 bit. +(8 bytes not 4). This needs to be taken into consideration when computing +branch offsets: the offset is relative to the start of the instruction, +which **includes** the SVP64 Prefix* + # Format and fields With element-width overrides being meaningless for Condition @@ -365,11 +370,6 @@ Vector. If `VLI=1` then VL would be set to 5 regardless of sz, due to being inclusive of the element actually being tested. -*Programming note: One important point is that SVP64 instructions are 64 bit. -(8 bytes not 4). This needs to be taken into consideration when computing -branch offsets: the offset is relative to the start of the instruction, -which includes the SVP64 Prefix* - # Boolean Logic combinations There are an extraordinary number of different combinations which