From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 2 Sep 2020 14:13:22 +0000 (+0100)
Subject: bug in carry32 handling in OP_CMP
X-Git-Tag: semi_working_ecp5~215
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33393954fd1742f4eddf86b03e9c639934c4a515;p=soc.git

bug in carry32 handling in OP_CMP
---

diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index f2e751d6..7f98c344 100644
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -100,7 +100,7 @@ class ALUMainStage(PipeModBase):
 
                 # this is supposed to be inverted (b-a, not a-b)
                 comb += a_n.eq(~a) # sigh a gets inverted
-                comb += carry_32.eq(add_o[33] ^ a_n[32] ^ b[32])
+                comb += carry_32.eq(add_o[33] ^ a[32] ^ b[32])
                 comb += carry_64.eq(add_o[65])
 
                 comb += zerolo.eq(~((a_n[0:32] ^ b[0:32]).bool()))