From: Ali Saidi <saidi@eecs.umich.edu>
Date: Thu, 1 Nov 2007 21:30:50 +0000 (-0400)
Subject: DRAM: Make latency parameters be Param.Latency instead of ints.
X-Git-Tag: m5_2.0_beta4~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=333ac6cc3221d449801ecd75a3f846b98acd5786;p=gem5.git

DRAM: Make latency parameters be Param.Latency instead of ints.

--HG--
extra : convert_revision : 553b86cc4653da089d7aa0045a3f3bdcabf6c4d8
---

diff --git a/src/mem/PhysicalMemory.py b/src/mem/PhysicalMemory.py
index 2ef3df7c1..99bd27f2b 100644
--- a/src/mem/PhysicalMemory.py
+++ b/src/mem/PhysicalMemory.py
@@ -46,12 +46,12 @@ class DRAMMemory(PhysicalMemory):
     mem_actpolicy = Param.String("open", "Open/Close policy")
     memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
     bus_width = Param.Int(16, "")
-    act_lat = Param.Int(2, "RAS to CAS delay")
-    cas_lat = Param.Int(1, "CAS delay")
-    war_lat = Param.Int(2, "write after read delay")
-    pre_lat = Param.Int(2, "precharge delay")
-    dpl_lat = Param.Int(2, "data in to precharge delay")
-    trc_lat = Param.Int(6, "row cycle delay")
+    act_lat = Param.Latency("2ns", "RAS to CAS delay")
+    cas_lat = Param.Latency("1ns", "CAS delay")
+    war_lat = Param.Latency("2ns", "write after read delay")
+    pre_lat = Param.Latency("2ns", "precharge delay")
+    dpl_lat = Param.Latency("2ns", "data in to precharge delay")
+    trc_lat = Param.Latency("6ns", "row cycle delay")
     num_banks = Param.Int(4, "Number of Banks")
     num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")