From: Daniel R. Carvalho Date: Thu, 11 Oct 2018 12:27:35 +0000 (+0200) Subject: mem-cache: Rename blk.cc/hh to cache_blk.cc/hh X-Git-Tag: v19.0.0.0~1596 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3341bccfe2ebec50a6a13af3f6a0bf711655fee9;p=gem5.git mem-cache: Rename blk.cc/hh to cache_blk.cc/hh Rename the files blk.cc and blk.hh to cache_blk.cc and cache_blk.hh to comply with the usual file-class naming rules. Change-Id: I8af45df3e4b8dd934fd9929ec914fb230cb2cb09 Signed-off-by: Daniel R. Carvalho Reviewed-on: https://gem5-review.googlesource.com/c/13416 Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris --- diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript index 24eea960e..8a4602b86 100644 --- a/src/mem/cache/SConscript +++ b/src/mem/cache/SConscript @@ -33,8 +33,8 @@ Import('*') SimObject('Cache.py') Source('base.cc') -Source('blk.cc') Source('cache.cc') +Source('cache_blk.cc') Source('mshr.cc') Source('mshr_queue.cc') Source('noncoherent_cache.cc') diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 4ebc52493..92748a38b 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -63,7 +63,7 @@ #include "debug/Cache.hh" #include "debug/CachePort.hh" #include "enums/Clusivity.hh" -#include "mem/cache/blk.hh" +#include "mem/cache/cache_blk.hh" #include "mem/cache/mshr_queue.hh" #include "mem/cache/tags/base.hh" #include "mem/cache/write_queue.hh" diff --git a/src/mem/cache/blk.cc b/src/mem/cache/blk.cc deleted file mode 100644 index 45bd9bfd4..000000000 --- a/src/mem/cache/blk.cc +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2012-2013 ARM Limited - * All rights reserved - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2007 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "mem/cache/blk.hh" - -#include "base/cprintf.hh" - -void -CacheBlk::insert(const Addr tag, const bool is_secure, - const int src_master_ID, const uint32_t task_ID) -{ - // Set block tag - this->tag = tag; - - // Set source requestor ID - srcMasterId = src_master_ID; - - // Set task ID - task_id = task_ID; - - // Set insertion tick as current tick - tickInserted = curTick(); - - // Insertion counts as a reference to the block - refCount = 1; - - // Set secure state - if (is_secure) { - status = BlkSecure; - } else { - status = 0; - } -} - -void -CacheBlkPrintWrapper::print(std::ostream &os, int verbosity, - const std::string &prefix) const -{ - ccprintf(os, "%sblk %c%c%c%c\n", prefix, - blk->isValid() ? 'V' : '-', - blk->isWritable() ? 'E' : '-', - blk->isDirty() ? 'M' : '-', - blk->isSecure() ? 'S' : '-'); -} - diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh deleted file mode 100644 index 6d91e5584..000000000 --- a/src/mem/cache/blk.hh +++ /dev/null @@ -1,466 +0,0 @@ -/* - * Copyright (c) 2012-2018 ARM Limited - * All rights reserved. - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Erik Hallnor - * Andreas Sandberg - */ - -/** @file - * Definitions of a simple cache block class. - */ - -#ifndef __MEM_CACHE_BLK_HH__ -#define __MEM_CACHE_BLK_HH__ - -#include -#include -#include -#include -#include - -#include "base/printable.hh" -#include "base/types.hh" -#include "mem/cache/replacement_policies/base.hh" -#include "mem/packet.hh" -#include "mem/request.hh" - -/** - * Cache block status bit assignments - */ -enum CacheBlkStatusBits : unsigned { - /** valid, readable */ - BlkValid = 0x01, - /** write permission */ - BlkWritable = 0x02, - /** read permission (yes, block can be valid but not readable) */ - BlkReadable = 0x04, - /** dirty (modified) */ - BlkDirty = 0x08, - /** block was a hardware prefetch yet unaccessed*/ - BlkHWPrefetched = 0x20, - /** block holds data from the secure memory space */ - BlkSecure = 0x40, -}; - -/** - * A Basic Cache block. - * Contains the tag, status, and a pointer to data. - */ -class CacheBlk : public ReplaceableEntry -{ - public: - /** Task Id associated with this block */ - uint32_t task_id; - - /** Data block tag value. */ - Addr tag; - /** - * Contains a copy of the data in this block for easy access. This is used - * for efficient execution when the data could be actually stored in - * another format (COW, compressed, sub-blocked, etc). In all cases the - * data stored here should be kept consistant with the actual data - * referenced by this block. - */ - uint8_t *data; - - /** block state: OR of CacheBlkStatusBit */ - typedef unsigned State; - - /** The current status of this block. @sa CacheBlockStatusBits */ - State status; - - /** Which curTick() will this block be accessible */ - Tick whenReady; - - /** Number of references to this block since it was brought in. */ - unsigned refCount; - - /** holds the source requestor ID for this block. */ - int srcMasterId; - - /** Tick on which the block was inserted in the cache. */ - Tick tickInserted; - - protected: - /** - * Represents that the indicated thread context has a "lock" on - * the block, in the LL/SC sense. - */ - class Lock { - public: - ContextID contextId; // locking context - Addr lowAddr; // low address of lock range - Addr highAddr; // high address of lock range - - // check for matching execution context, and an address that - // is within the lock - bool matches(const RequestPtr &req) const - { - Addr req_low = req->getPaddr(); - Addr req_high = req_low + req->getSize() -1; - return (contextId == req->contextId()) && - (req_low >= lowAddr) && (req_high <= highAddr); - } - - // check if a request is intersecting and thus invalidating the lock - bool intersects(const RequestPtr &req) const - { - Addr req_low = req->getPaddr(); - Addr req_high = req_low + req->getSize() - 1; - - return (req_low <= highAddr) && (req_high >= lowAddr); - } - - Lock(const RequestPtr &req) - : contextId(req->contextId()), - lowAddr(req->getPaddr()), - highAddr(lowAddr + req->getSize() - 1) - { - } - }; - - /** List of thread contexts that have performed a load-locked (LL) - * on the block since the last store. */ - std::list lockList; - - public: - CacheBlk() : data(nullptr) - { - invalidate(); - } - - CacheBlk(const CacheBlk&) = delete; - CacheBlk& operator=(const CacheBlk&) = delete; - virtual ~CacheBlk() {}; - - /** - * Checks the write permissions of this block. - * @return True if the block is writable. - */ - bool isWritable() const - { - const State needed_bits = BlkWritable | BlkValid; - return (status & needed_bits) == needed_bits; - } - - /** - * Checks the read permissions of this block. Note that a block - * can be valid but not readable if there is an outstanding write - * upgrade miss. - * @return True if the block is readable. - */ - bool isReadable() const - { - const State needed_bits = BlkReadable | BlkValid; - return (status & needed_bits) == needed_bits; - } - - /** - * Checks that a block is valid. - * @return True if the block is valid. - */ - bool isValid() const - { - return (status & BlkValid) != 0; - } - - /** - * Invalidate the block and clear all state. - */ - virtual void invalidate() - { - tag = MaxAddr; - task_id = ContextSwitchTaskId::Unknown; - status = 0; - whenReady = MaxTick; - refCount = 0; - srcMasterId = Request::invldMasterId; - tickInserted = MaxTick; - lockList.clear(); - } - - /** - * Check to see if a block has been written. - * @return True if the block is dirty. - */ - bool isDirty() const - { - return (status & BlkDirty) != 0; - } - - /** - * Check if this block was the result of a hardware prefetch, yet to - * be touched. - * @return True if the block was a hardware prefetch, unaccesed. - */ - bool wasPrefetched() const - { - return (status & BlkHWPrefetched) != 0; - } - - /** - * Check if this block holds data from the secure memory space. - * @return True if the block holds data from the secure memory space. - */ - bool isSecure() const - { - return (status & BlkSecure) != 0; - } - - /** - * Set member variables when a block insertion occurs. Resets reference - * count to 1 (the insertion counts as a reference), and touch block if - * it hadn't been touched previously. Sets the insertion tick to the - * current tick. Does not make block valid. - * - * @param tag Block address tag. - * @param is_secure Whether the block is in secure space or not. - * @param src_master_ID The source requestor ID. - * @param task_ID The new task ID. - */ - virtual void insert(const Addr tag, const bool is_secure, - const int src_master_ID, const uint32_t task_ID); - - /** - * Track the fact that a local locked was issued to the - * block. Invalidate any previous LL to the same address. - */ - void trackLoadLocked(PacketPtr pkt) - { - assert(pkt->isLLSC()); - auto l = lockList.begin(); - while (l != lockList.end()) { - if (l->intersects(pkt->req)) - l = lockList.erase(l); - else - ++l; - } - - lockList.emplace_front(pkt->req); - } - - /** - * Clear the any load lock that intersect the request, and is from - * a different context. - */ - void clearLoadLocks(const RequestPtr &req) - { - auto l = lockList.begin(); - while (l != lockList.end()) { - if (l->intersects(req) && l->contextId != req->contextId()) { - l = lockList.erase(l); - } else { - ++l; - } - } - } - - /** - * Pretty-print tag, set and way, and interpret state bits to readable form - * including mapping to a MOESI state. - * - * @return string with basic state information - */ - virtual std::string print() const - { - /** - * state M O E S I - * writable 1 0 1 0 0 - * dirty 1 1 0 0 0 - * valid 1 1 1 1 0 - * - * state writable dirty valid - * M 1 1 1 - * O 0 1 1 - * E 1 0 1 - * S 0 0 1 - * I 0 0 0 - * - * Note that only one cache ever has a block in Modified or - * Owned state, i.e., only one cache owns the block, or - * equivalently has the BlkDirty bit set. However, multiple - * caches on the same path to memory can have a block in the - * Exclusive state (despite the name). Exclusive means this - * cache has the only copy at this level of the hierarchy, - * i.e., there may be copies in caches above this cache (in - * various states), but there are no peers that have copies on - * this branch of the hierarchy, and no caches at or above - * this level on any other branch have copies either. - **/ - unsigned state = isWritable() << 2 | isDirty() << 1 | isValid(); - char s = '?'; - switch (state) { - case 0b111: s = 'M'; break; - case 0b011: s = 'O'; break; - case 0b101: s = 'E'; break; - case 0b001: s = 'S'; break; - case 0b000: s = 'I'; break; - default: s = 'T'; break; // @TODO add other types - } - return csprintf("state: %x (%c) valid: %d writable: %d readable: %d " - "dirty: %d | tag: %#x set: %#x way: %#x", status, s, - isValid(), isWritable(), isReadable(), isDirty(), tag, - getSet(), getWay()); - } - - /** - * Handle interaction of load-locked operations and stores. - * @return True if write should proceed, false otherwise. Returns - * false only in the case of a failed store conditional. - */ - bool checkWrite(PacketPtr pkt) - { - assert(pkt->isWrite()); - - // common case - if (!pkt->isLLSC() && lockList.empty()) - return true; - - const RequestPtr &req = pkt->req; - - if (pkt->isLLSC()) { - // it's a store conditional... have to check for matching - // load locked. - bool success = false; - - auto l = lockList.begin(); - while (!success && l != lockList.end()) { - if (l->matches(pkt->req)) { - // it's a store conditional, and as far as the - // memory system can tell, the requesting - // context's lock is still valid. - success = true; - lockList.erase(l); - } else { - ++l; - } - } - - req->setExtraData(success ? 1 : 0); - // clear any intersected locks from other contexts (our LL - // should already have cleared them) - clearLoadLocks(req); - return success; - } else { - // a normal write, if there is any lock not from this - // context we clear the list, thus for a private cache we - // never clear locks on normal writes - clearLoadLocks(req); - return true; - } - } -}; - -/** - * Special instance of CacheBlk for use with tempBlk that deals with its - * block address regeneration. - * @sa Cache - */ -class TempCacheBlk final : public CacheBlk -{ - private: - /** - * Copy of the block's address, used to regenerate tempBlock's address. - */ - Addr _addr; - - public: - /** - * Creates a temporary cache block, with its own storage. - * @param size The size (in bytes) of this cache block. - */ - TempCacheBlk(unsigned size) : CacheBlk() - { - data = new uint8_t[size]; - } - TempCacheBlk(const TempCacheBlk&) = delete; - TempCacheBlk& operator=(const TempCacheBlk&) = delete; - ~TempCacheBlk() { delete [] data; }; - - /** - * Invalidate the block and clear all state. - */ - void invalidate() override { - CacheBlk::invalidate(); - - _addr = MaxAddr; - } - - void insert(const Addr addr, const bool is_secure, - const int src_master_ID=0, const uint32_t task_ID=0) override - { - // Set block address - _addr = addr; - - // Set secure state - if (is_secure) { - status = BlkSecure; - } else { - status = 0; - } - } - - /** - * Get block's address. - * - * @return addr Address value. - */ - Addr getAddr() const - { - return _addr; - } -}; - -/** - * Simple class to provide virtual print() method on cache blocks - * without allocating a vtable pointer for every single cache block. - * Just wrap the CacheBlk object in an instance of this before passing - * to a function that requires a Printable object. - */ -class CacheBlkPrintWrapper : public Printable -{ - CacheBlk *blk; - public: - CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {} - virtual ~CacheBlkPrintWrapper() {} - void print(std::ostream &o, int verbosity = 0, - const std::string &prefix = "") const; -}; - -#endif //__MEM_CACHE_BLK_HH__ diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index 1b5316383..116b543cc 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -64,7 +64,7 @@ #include "debug/CacheTags.hh" #include "debug/CacheVerbose.hh" #include "enums/Clusivity.hh" -#include "mem/cache/blk.hh" +#include "mem/cache/cache_blk.hh" #include "mem/cache/mshr.hh" #include "mem/cache/tags/base.hh" #include "mem/cache/write_queue_entry.hh" diff --git a/src/mem/cache/cache_blk.cc b/src/mem/cache/cache_blk.cc new file mode 100644 index 000000000..a77fc630a --- /dev/null +++ b/src/mem/cache/cache_blk.cc @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2012-2013 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2007 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "mem/cache/cache_blk.hh" + +#include "base/cprintf.hh" + +void +CacheBlk::insert(const Addr tag, const bool is_secure, + const int src_master_ID, const uint32_t task_ID) +{ + // Set block tag + this->tag = tag; + + // Set source requestor ID + srcMasterId = src_master_ID; + + // Set task ID + task_id = task_ID; + + // Set insertion tick as current tick + tickInserted = curTick(); + + // Insertion counts as a reference to the block + refCount = 1; + + // Set secure state + if (is_secure) { + status = BlkSecure; + } else { + status = 0; + } +} + +void +CacheBlkPrintWrapper::print(std::ostream &os, int verbosity, + const std::string &prefix) const +{ + ccprintf(os, "%sblk %c%c%c%c\n", prefix, + blk->isValid() ? 'V' : '-', + blk->isWritable() ? 'E' : '-', + blk->isDirty() ? 'M' : '-', + blk->isSecure() ? 'S' : '-'); +} + diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh new file mode 100644 index 000000000..80983a637 --- /dev/null +++ b/src/mem/cache/cache_blk.hh @@ -0,0 +1,466 @@ +/* + * Copyright (c) 2012-2018 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Erik Hallnor + * Andreas Sandberg + */ + +/** @file + * Definitions of a simple cache block class. + */ + +#ifndef __MEM_CACHE_CACHE_BLK_HH__ +#define __MEM_CACHE_CACHE_BLK_HH__ + +#include +#include +#include +#include +#include + +#include "base/printable.hh" +#include "base/types.hh" +#include "mem/cache/replacement_policies/base.hh" +#include "mem/packet.hh" +#include "mem/request.hh" + +/** + * Cache block status bit assignments + */ +enum CacheBlkStatusBits : unsigned { + /** valid, readable */ + BlkValid = 0x01, + /** write permission */ + BlkWritable = 0x02, + /** read permission (yes, block can be valid but not readable) */ + BlkReadable = 0x04, + /** dirty (modified) */ + BlkDirty = 0x08, + /** block was a hardware prefetch yet unaccessed*/ + BlkHWPrefetched = 0x20, + /** block holds data from the secure memory space */ + BlkSecure = 0x40, +}; + +/** + * A Basic Cache block. + * Contains the tag, status, and a pointer to data. + */ +class CacheBlk : public ReplaceableEntry +{ + public: + /** Task Id associated with this block */ + uint32_t task_id; + + /** Data block tag value. */ + Addr tag; + /** + * Contains a copy of the data in this block for easy access. This is used + * for efficient execution when the data could be actually stored in + * another format (COW, compressed, sub-blocked, etc). In all cases the + * data stored here should be kept consistant with the actual data + * referenced by this block. + */ + uint8_t *data; + + /** block state: OR of CacheBlkStatusBit */ + typedef unsigned State; + + /** The current status of this block. @sa CacheBlockStatusBits */ + State status; + + /** Which curTick() will this block be accessible */ + Tick whenReady; + + /** Number of references to this block since it was brought in. */ + unsigned refCount; + + /** holds the source requestor ID for this block. */ + int srcMasterId; + + /** Tick on which the block was inserted in the cache. */ + Tick tickInserted; + + protected: + /** + * Represents that the indicated thread context has a "lock" on + * the block, in the LL/SC sense. + */ + class Lock { + public: + ContextID contextId; // locking context + Addr lowAddr; // low address of lock range + Addr highAddr; // high address of lock range + + // check for matching execution context, and an address that + // is within the lock + bool matches(const RequestPtr &req) const + { + Addr req_low = req->getPaddr(); + Addr req_high = req_low + req->getSize() -1; + return (contextId == req->contextId()) && + (req_low >= lowAddr) && (req_high <= highAddr); + } + + // check if a request is intersecting and thus invalidating the lock + bool intersects(const RequestPtr &req) const + { + Addr req_low = req->getPaddr(); + Addr req_high = req_low + req->getSize() - 1; + + return (req_low <= highAddr) && (req_high >= lowAddr); + } + + Lock(const RequestPtr &req) + : contextId(req->contextId()), + lowAddr(req->getPaddr()), + highAddr(lowAddr + req->getSize() - 1) + { + } + }; + + /** List of thread contexts that have performed a load-locked (LL) + * on the block since the last store. */ + std::list lockList; + + public: + CacheBlk() : data(nullptr) + { + invalidate(); + } + + CacheBlk(const CacheBlk&) = delete; + CacheBlk& operator=(const CacheBlk&) = delete; + virtual ~CacheBlk() {}; + + /** + * Checks the write permissions of this block. + * @return True if the block is writable. + */ + bool isWritable() const + { + const State needed_bits = BlkWritable | BlkValid; + return (status & needed_bits) == needed_bits; + } + + /** + * Checks the read permissions of this block. Note that a block + * can be valid but not readable if there is an outstanding write + * upgrade miss. + * @return True if the block is readable. + */ + bool isReadable() const + { + const State needed_bits = BlkReadable | BlkValid; + return (status & needed_bits) == needed_bits; + } + + /** + * Checks that a block is valid. + * @return True if the block is valid. + */ + bool isValid() const + { + return (status & BlkValid) != 0; + } + + /** + * Invalidate the block and clear all state. + */ + virtual void invalidate() + { + tag = MaxAddr; + task_id = ContextSwitchTaskId::Unknown; + status = 0; + whenReady = MaxTick; + refCount = 0; + srcMasterId = Request::invldMasterId; + tickInserted = MaxTick; + lockList.clear(); + } + + /** + * Check to see if a block has been written. + * @return True if the block is dirty. + */ + bool isDirty() const + { + return (status & BlkDirty) != 0; + } + + /** + * Check if this block was the result of a hardware prefetch, yet to + * be touched. + * @return True if the block was a hardware prefetch, unaccesed. + */ + bool wasPrefetched() const + { + return (status & BlkHWPrefetched) != 0; + } + + /** + * Check if this block holds data from the secure memory space. + * @return True if the block holds data from the secure memory space. + */ + bool isSecure() const + { + return (status & BlkSecure) != 0; + } + + /** + * Set member variables when a block insertion occurs. Resets reference + * count to 1 (the insertion counts as a reference), and touch block if + * it hadn't been touched previously. Sets the insertion tick to the + * current tick. Does not make block valid. + * + * @param tag Block address tag. + * @param is_secure Whether the block is in secure space or not. + * @param src_master_ID The source requestor ID. + * @param task_ID The new task ID. + */ + virtual void insert(const Addr tag, const bool is_secure, + const int src_master_ID, const uint32_t task_ID); + + /** + * Track the fact that a local locked was issued to the + * block. Invalidate any previous LL to the same address. + */ + void trackLoadLocked(PacketPtr pkt) + { + assert(pkt->isLLSC()); + auto l = lockList.begin(); + while (l != lockList.end()) { + if (l->intersects(pkt->req)) + l = lockList.erase(l); + else + ++l; + } + + lockList.emplace_front(pkt->req); + } + + /** + * Clear the any load lock that intersect the request, and is from + * a different context. + */ + void clearLoadLocks(const RequestPtr &req) + { + auto l = lockList.begin(); + while (l != lockList.end()) { + if (l->intersects(req) && l->contextId != req->contextId()) { + l = lockList.erase(l); + } else { + ++l; + } + } + } + + /** + * Pretty-print tag, set and way, and interpret state bits to readable form + * including mapping to a MOESI state. + * + * @return string with basic state information + */ + virtual std::string print() const + { + /** + * state M O E S I + * writable 1 0 1 0 0 + * dirty 1 1 0 0 0 + * valid 1 1 1 1 0 + * + * state writable dirty valid + * M 1 1 1 + * O 0 1 1 + * E 1 0 1 + * S 0 0 1 + * I 0 0 0 + * + * Note that only one cache ever has a block in Modified or + * Owned state, i.e., only one cache owns the block, or + * equivalently has the BlkDirty bit set. However, multiple + * caches on the same path to memory can have a block in the + * Exclusive state (despite the name). Exclusive means this + * cache has the only copy at this level of the hierarchy, + * i.e., there may be copies in caches above this cache (in + * various states), but there are no peers that have copies on + * this branch of the hierarchy, and no caches at or above + * this level on any other branch have copies either. + **/ + unsigned state = isWritable() << 2 | isDirty() << 1 | isValid(); + char s = '?'; + switch (state) { + case 0b111: s = 'M'; break; + case 0b011: s = 'O'; break; + case 0b101: s = 'E'; break; + case 0b001: s = 'S'; break; + case 0b000: s = 'I'; break; + default: s = 'T'; break; // @TODO add other types + } + return csprintf("state: %x (%c) valid: %d writable: %d readable: %d " + "dirty: %d | tag: %#x set: %#x way: %#x", status, s, + isValid(), isWritable(), isReadable(), isDirty(), tag, + getSet(), getWay()); + } + + /** + * Handle interaction of load-locked operations and stores. + * @return True if write should proceed, false otherwise. Returns + * false only in the case of a failed store conditional. + */ + bool checkWrite(PacketPtr pkt) + { + assert(pkt->isWrite()); + + // common case + if (!pkt->isLLSC() && lockList.empty()) + return true; + + const RequestPtr &req = pkt->req; + + if (pkt->isLLSC()) { + // it's a store conditional... have to check for matching + // load locked. + bool success = false; + + auto l = lockList.begin(); + while (!success && l != lockList.end()) { + if (l->matches(pkt->req)) { + // it's a store conditional, and as far as the + // memory system can tell, the requesting + // context's lock is still valid. + success = true; + lockList.erase(l); + } else { + ++l; + } + } + + req->setExtraData(success ? 1 : 0); + // clear any intersected locks from other contexts (our LL + // should already have cleared them) + clearLoadLocks(req); + return success; + } else { + // a normal write, if there is any lock not from this + // context we clear the list, thus for a private cache we + // never clear locks on normal writes + clearLoadLocks(req); + return true; + } + } +}; + +/** + * Special instance of CacheBlk for use with tempBlk that deals with its + * block address regeneration. + * @sa Cache + */ +class TempCacheBlk final : public CacheBlk +{ + private: + /** + * Copy of the block's address, used to regenerate tempBlock's address. + */ + Addr _addr; + + public: + /** + * Creates a temporary cache block, with its own storage. + * @param size The size (in bytes) of this cache block. + */ + TempCacheBlk(unsigned size) : CacheBlk() + { + data = new uint8_t[size]; + } + TempCacheBlk(const TempCacheBlk&) = delete; + TempCacheBlk& operator=(const TempCacheBlk&) = delete; + ~TempCacheBlk() { delete [] data; }; + + /** + * Invalidate the block and clear all state. + */ + void invalidate() override { + CacheBlk::invalidate(); + + _addr = MaxAddr; + } + + void insert(const Addr addr, const bool is_secure, + const int src_master_ID=0, const uint32_t task_ID=0) override + { + // Set block address + _addr = addr; + + // Set secure state + if (is_secure) { + status = BlkSecure; + } else { + status = 0; + } + } + + /** + * Get block's address. + * + * @return addr Address value. + */ + Addr getAddr() const + { + return _addr; + } +}; + +/** + * Simple class to provide virtual print() method on cache blocks + * without allocating a vtable pointer for every single cache block. + * Just wrap the CacheBlk object in an instance of this before passing + * to a function that requires a Printable object. + */ +class CacheBlkPrintWrapper : public Printable +{ + CacheBlk *blk; + public: + CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {} + virtual ~CacheBlkPrintWrapper() {} + void print(std::ostream &o, int verbosity = 0, + const std::string &prefix = "") const; +}; + +#endif //__MEM_CACHE_CACHE_BLK_HH__ diff --git a/src/mem/cache/noncoherent_cache.cc b/src/mem/cache/noncoherent_cache.cc index fb8193a99..b4ffed786 100644 --- a/src/mem/cache/noncoherent_cache.cc +++ b/src/mem/cache/noncoherent_cache.cc @@ -60,7 +60,7 @@ #include "base/trace.hh" #include "base/types.hh" #include "debug/Cache.hh" -#include "mem/cache/blk.hh" +#include "mem/cache/cache_blk.hh" #include "mem/cache/mshr.hh" #include "params/NoncoherentCache.hh" diff --git a/src/mem/cache/sector_blk.hh b/src/mem/cache/sector_blk.hh index 66d83a230..3d09d2b49 100644 --- a/src/mem/cache/sector_blk.hh +++ b/src/mem/cache/sector_blk.hh @@ -38,7 +38,7 @@ #include -#include "mem/cache/blk.hh" +#include "mem/cache/cache_blk.hh" #include "mem/cache/replacement_policies/base.hh" class SectorBlk; diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh index 589de37c0..257b1bd29 100644 --- a/src/mem/cache/tags/base.hh +++ b/src/mem/cache/tags/base.hh @@ -57,7 +57,7 @@ #include "base/logging.hh" #include "base/statistics.hh" #include "base/types.hh" -#include "mem/cache/blk.hh" +#include "mem/cache/cache_blk.hh" #include "params/BaseTags.hh" #include "sim/clocked_object.hh" diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh index 11c0c8d11..f73a5d92f 100644 --- a/src/mem/cache/tags/base_set_assoc.hh +++ b/src/mem/cache/tags/base_set_assoc.hh @@ -55,7 +55,7 @@ #include "base/logging.hh" #include "base/types.hh" #include "mem/cache/base.hh" -#include "mem/cache/blk.hh" +#include "mem/cache/cache_blk.hh" #include "mem/cache/replacement_policies/base.hh" #include "mem/cache/tags/base.hh" #include "mem/cache/tags/indexing_policies/base.hh" diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index c2f983468..15043995f 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -60,7 +60,7 @@ #include "base/logging.hh" #include "base/statistics.hh" #include "base/types.hh" -#include "mem/cache/blk.hh" +#include "mem/cache/cache_blk.hh" #include "mem/cache/tags/base.hh" #include "params/FALRU.hh"