From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 07:53:54 +0000 (+0200)
Subject: Removed top module where not needed
X-Git-Tag: working-ls180~989^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3358b2f18597c59ee3cac5f123f954ca79e0baad;p=yosys.git

Removed top module where not needed
---

diff --git a/tests/ecp5/fsm.v b/tests/ecp5/fsm.v
index 0605bd102..368fbaace 100644
--- a/tests/ecp5/fsm.v
+++ b/tests/ecp5/fsm.v
@@ -52,22 +52,4 @@
  endcase
  end
 
- endmodule
-
- module top (
-input clk,
-input rst,
-input a,
-input b,
-output g0,
-output g1
-);
-
-fsm u_fsm ( .clock(clk),
-            .reset(rst),
-            .req_0(a),
-            .req_1(b),
-            .gnt_0(g0),
-            .gnt_1(g1));
-
 endmodule
diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys
index 6368edc57..ded91e5f7 100644
--- a/tests/ecp5/fsm.ys
+++ b/tests/ecp5/fsm.ys
@@ -1,10 +1,10 @@
 read_verilog fsm.v
-hierarchy -top top
+hierarchy -top fsm
 proc
 flatten
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 select -assert-count 1 t:L6MUX21
 select -assert-count 13 t:LUT4
 select -assert-count 5 t:PFUMX
diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v
index 870a02584..90dd314e4 100644
--- a/tests/ecp5/tribuf.v
+++ b/tests/ecp5/tribuf.v
@@ -6,18 +6,3 @@ module tristate (en, i, o);
 	assign o = en ? i : 1'bz;
 
 endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
-endmodule
diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys
index f454a0c02..a6e9c9598 100644
--- a/tests/ecp5/tribuf.ys
+++ b/tests/ecp5/tribuf.ys
@@ -1,9 +1,9 @@
 read_verilog tribuf.v
-hierarchy -top top
+hierarchy -top tristate
 proc
 flatten
 equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D