From: Luke Kenneth Casson Leighton Date: Sat, 15 Apr 2023 16:34:15 +0000 (+0100) Subject: mode bits name field correctly X-Git-Tag: opf_rfc_ls009_v1~67 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3363b0b85ef2a5ffdd5c45ef2e54ba24fc723d05;p=libreriscv.git mode bits name field correctly --- diff --git a/openpower/sv/rfc/ls009.mdwn b/openpower/sv/rfc/ls009.mdwn index be14b828e..886500e51 100644 --- a/openpower/sv/rfc/ls009.mdwn +++ b/openpower/sv/rfc/ls009.mdwn @@ -610,7 +610,7 @@ disabled: the register's elements are a linear (1D) vector. |31.30|29..28 |27..24| 23..21 | 20..18 | 17..12 |11..6 |5..0 | Mode | |---- |------ |------| ------ | ------- | ------- |----- |----- | ----- | -|0b00 |skip |offset| invxyz | permute | zdimsz |ydimsz|xdimsz|Matrix | +|mode |skip |offset| invxyz | permute | zdimsz |ydimsz|xdimsz|Matrix | |0b00 |elwidth|offset|sk1/invxy|0b110/0b111|SVGPR|ydimsz|xdimsz|Indexed| |0b01 |submode|offset| invxyz | submode2| zdimsz |mode |xdimsz|DCT/FFT| |0b10 |submode|offset| invxyz | rsvd | rsvd |rsvd |xdimsz|Preduce|