From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 7 May 2019 17:55:36 +0000 (+0200)
Subject: Fix handling of partial init attributes in write_verilog, fixes #997
X-Git-Tag: yosys-0.9~137
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33738c174560c718723b6c860af002d1a8a91cea;p=yosys.git

Fix handling of partial init attributes in write_verilog, fixes #997

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 9fd4ccbc8..827af5d85 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1618,7 +1618,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 			SigSpec sig = active_sigmap(wire);
 			Const val = wire->attributes.at("\\init");
 			for (int i = 0; i < GetSize(sig) && i < GetSize(val); i++)
-				active_initdata[sig[i]] = val.bits.at(i);
+				if (val[i] == State::S0 || val[i] == State::S1)
+					active_initdata[sig[i]] = val[i];
 		}
 
 	if (!module->processes.empty())