From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 16 Apr 2021 00:41:42 +0000 (+0100)
Subject: corrections to wishbone test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3380624385a87e3b50016c350b0314c80052e7d3;p=soc-cocotb-sim.git

corrections to wishbone test
---

diff --git a/ls180/post_pnr/cocotb/test.py b/ls180/post_pnr/cocotb/test.py
index 9bf57fd..2c1174d 100644
--- a/ls180/post_pnr/cocotb/test.py
+++ b/ls180/post_pnr/cocotb/test.py
@@ -190,7 +190,7 @@ def wishbone_basic(dut):
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "000000000000000000000000000000"
+    assert master.result.binstr == "000000000000000000000000000011"
 
     # Do read and write
     yield master.load_ir(cmd_MEMREADWRITE)
@@ -226,22 +226,22 @@ def wishbone_basic(dut):
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    #assert master.result.binstr == "10101010" * 4
+    assert master.result.binstr == "10101010" * 4
 
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    #assert master.result.binstr == "01010101" * 4
+    assert master.result.binstr == "01010101" * 4
 
     # Load the memory address
     yield master.load_ir(cmd_MEMADDRESS) # MEMADDR
     dut._log.info("Loading address")
 
-    data_in.binstr = "0000000000000000000000000000001"
+    data_in.binstr = "000000000000000000000000000001"
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    #assert master.result.binstr == "000000000000000000000000000010"
+    assert master.result.binstr == "000000000000000000000000000010"
 
     # Do read
     yield master.load_ir(cmd_MEMREAD) # MEMREAD
@@ -251,14 +251,14 @@ def wishbone_basic(dut):
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    #assert master.result.binstr == "10101010" * 4
+    assert master.result.binstr == "10101010" * 4
 
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    #assert master.result.binstr == "01010101" * 4
+    assert master.result.binstr == "01010101" * 4
 
-    dut._log.info("{!r}".format(wbmem))
+    #dut._log.info("{!r}".format(wbmem))
 
 
 # demo / debug how to get boundary scan names. run "python3 test.py"