From: Cole Poirier Date: Tue, 28 Jul 2020 20:21:38 +0000 (-0700) Subject: Add svg version of 180nm_single_core_test_asic_memlayout to wiki X-Git-Tag: convert-csv-opcode-to-binary~2320 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33947b57c9b9965f2b11a17f77e8fad7115e9343;p=libreriscv.git Add svg version of 180nm_single_core_test_asic_memlayout to wiki --- diff --git a/3d_gpu/180nm_single_core_test_asic_memlayout_F1.svg b/3d_gpu/180nm_single_core_test_asic_memlayout_F1.svg new file mode 100644 index 000000000..b756c3a73 --- /dev/null +++ b/3d_gpu/180nm_single_core_test_asic_memlayout_F1.svg @@ -0,0 +1,3902 @@ + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + Wishbone D/64 + + + + + + + + + + + + + + + + + RGB/TTL + QSPI + DRAM + SDMMC + NO L2 + + + + FU0 + FU1 + FU3 + FU4 + FU5 + FU6 + FU2 + FU7 + Addr[12:48] + Addr[4]=0 + Bytemask[0:15] + A[5:11] + Data[0:15] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Addr[4]=1 + Bytemask[0:15] + A[5:11] + Data[0:15] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Addr[12:48] + Single Entry + + + Addr[5:11] + Double Entry + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L1 Odd + (Addr[4]=1) + + Wishbone D/64 + + + + + + + D/128 + D/64 + + + + + + + + + + + + + D/128 + DataMerger2 + + + + PriorityPicker + + + + + + + 128 to 64 + bit Arbiters + + + + + + + + + + + + Select FU0-FU7 >= N + Merge Bytemask > N + + DataMerger + + + + + + + + + L1 Even + (Addr[4]=0) + + Wishbone D/64 + D/128 + D/128 + D/64 + + + + + + + + + + + + + DataMerger1 + + + + + + + + Addr[5:] + Bytemask + Data + Addr[4]? + + + + + + + + + + + + + + + + + + + + + + + + + + Addr + Len + Data + + LDSTCU1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PortInterface(Even) + PortInterface(Odd) + LDSTSplitter + PortInterface + + + Addr + Len + Data + + LDSTCU2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PortInterface(Even) + PortInterface(Odd) + LDSTSplitter + PortInterface + + + Addr + Len + Data + + LDSTCU3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PortInterface(Even) + PortInterface(Odd) + LDSTSplitter + PortInterface + + + Addr + Len + Data + + LDSTCU4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PortInterface(Even) + PortInterface(Odd) + LDSTSplitter + PortInterface + + + Addr + Len + Data + + LDSTCU5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PortInterface(Even) + PortInterface(Odd) + LDSTSplitter + PortInterface + + + Addr + Len + Data + + LDSTCU6 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PortInterface(Even) + PortInterface(Odd) + LDSTSplitter + PortInterface + + + Addr + Len + Data + + LDSTCU7 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PortInterface(Even) + PortInterface(Odd) + LDSTSplitter + PortInterface + + + + + + + + + + + + + + + + + + + LDSTCU0 + Addr + Len + Data + + + + + PortInterface + + + Addr[5:] + Bytemask + Data + +