From: Andreas Hansson <andreas.hansson@arm.com>
Date: Thu, 27 Jun 2013 09:49:49 +0000 (-0400)
Subject: mem: Align cache timing to clock edges
X-Git-Tag: stable_2013_10_14~20
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33a8d777add840cae1938a1fbe9e155840769a38;p=gem5.git

mem: Align cache timing to clock edges

This patch changes the cache timing calculations such that the results
are aligned to clock edges.

Plenty stats change as a results of this patch.
---

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index f697f84e4..7098dbfd3 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -929,7 +929,7 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
                 // responseLatency is the latency of the return path
                 // from lower level caches/memory to an upper level cache or
                 // the core.
-                completion_time = curTick() + responseLatency * clockPeriod() +
+                completion_time = clockEdge(responseLatency) +
                     (transfer_offset ? pkt->busLastWordDelay :
                      pkt->busFirstWordDelay);
 
@@ -946,14 +946,14 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
                 // responseLatency is the latency of the return path
                 // from lower level caches/memory to an upper level cache or
                 // the core.
-                completion_time = curTick() + responseLatency * clockPeriod() +
+                completion_time = clockEdge(responseLatency) +
                     pkt->busLastWordDelay;
                 target->pkt->req->setExtraData(0);
             } else {
                 // not a cache fill, just forwarding response
                 // responseLatency is the latency of the return path
                 // from lower level cahces/memory to the core.
-                completion_time = curTick() + responseLatency * clockPeriod() +
+                completion_time = clockEdge(responseLatency) +
                     pkt->busLastWordDelay;
                 if (pkt->isRead() && !is_error) {
                     target->pkt->setData(pkt->getPtr<uint8_t>());
@@ -1021,7 +1021,7 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
         }
         mq = mshr->queue;
         mq->markPending(mshr);
-        requestMemSideBus((RequestCause)mq->index, curTick() +
+        requestMemSideBus((RequestCause)mq->index, clockEdge() +
                           pkt->busLastWordDelay);
     } else {
         mq->deallocate(mshr);
@@ -1257,7 +1257,7 @@ Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
         std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
     }
 
-    blk->whenReady = curTick() + responseLatency * clockPeriod() +
+    blk->whenReady = clockEdge() + responseLatency * clockPeriod() +
         pkt->busLastWordDelay;
 
     return blk;