From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 24 May 2020 15:48:23 +0000 (-0700)
Subject: xaiger: add testcase
X-Git-Tag: working-ls180~540^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33b03ce904f6810437e27ca7a6df4fb1e966fc23;p=yosys.git

xaiger: add testcase
---

diff --git a/tests/various/xaiger.ys b/tests/various/xaiger.ys
new file mode 100644
index 000000000..f612d2e18
--- /dev/null
+++ b/tests/various/xaiger.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top(input a, b, output c);
+bb #(1) bb();
+endmodule
+
+module bb(input a, b, output c);
+parameter p = 0;
+assign c = a ^ b;
+endmodule
+EOT
+blackbox bb
+hierarchy
+write_xaiger /dev/null