From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 11 Mar 2019 12:54:57 +0000 (+0000)
Subject: add inputgroup test
X-Git-Tag: ls180-24jan2020~1691
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33b30ebf9210e7a3c03d3babc73ad4ed12b8685e;p=ieee754fpu.git

add inputgroup test
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 74ce502d..660b0794 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -105,9 +105,9 @@ class InputGroup:
         for i in range(self.num_rows):
             in_ready.append(self.rs[i].ready)
         m.d.comb += pe.i.eq(Cat(*in_ready))
-        m.d.comb += self.out_op.stb.eq(pe.n) # strobe-out when encoder active
+        m.d.comb += self.out_op.stb.eq(~pe.n) # strobe-out when encoder active
 
-        with m.If(pe.n):
+        with m.If(self.out_op.trigger):
             m.d.sync += self.mid.eq(pe.o)
             for j in range(self.num_ops):
                 m.d.sync += self.out_op.v[j].eq(self.rs[pe.o].out_op[j])
diff --git a/src/add/test_inputgroup.py b/src/add/test_inputgroup.py
new file mode 100644
index 00000000..c4be8004
--- /dev/null
+++ b/src/add/test_inputgroup.py
@@ -0,0 +1,68 @@
+from random import randint
+from nmigen import Module, Signal
+from nmigen.compat.sim import run_simulation
+from nmigen.cli import verilog
+
+from nmigen_add_experiment import InputGroup
+
+
+def testbench(dut):
+    stb = yield dut.out_op.stb
+    assert stb == 0
+    ack = yield dut.out_op.ack
+    assert ack == 0
+
+    # set row 1 input 0
+    yield dut.rs[1].in_op[0].eq(5)
+    yield dut.rs[1].stb.eq(0b01) # strobe indicate 1st op ready
+    yield dut.rs[1].ack.eq(1)
+    yield
+    yield
+
+    # check row 1 output (should be inactive)
+    decode = yield dut.rs[1].out_decode
+    assert decode == 0
+    op0 = yield dut.rs[1].out_op[0]
+    op1 = yield dut.rs[1].out_op[1]
+    assert op0 == 0 and op1 == 0
+
+    # output should be inactive
+    out_stb = yield dut.out_op.stb
+    assert out_stb == 0
+
+    # set row 0 input 1
+    yield dut.rs[1].in_op[1].eq(6)
+    yield dut.rs[1].stb.eq(0b11) # strobe indicate both ops ready
+    yield
+    yield
+
+    # row 0 output should be active
+    decode = yield dut.rs[1].out_decode
+    assert decode == 1
+    op0 = yield dut.rs[1].out_op[0]
+    op1 = yield dut.rs[1].out_op[1]
+    assert op0 == 5 and op1 == 6
+
+    # output should be active, MID should be 0 until "ack" is set
+    out_stb = yield dut.out_op.stb
+    assert out_stb == 1
+    out_mid = yield dut.mid
+    assert out_mid == 0
+
+    yield dut.out_op.ack.eq(1)
+    yield
+    yield
+    yield
+    yield
+
+    op0 = yield dut.out_op.v[0]
+    op1 = yield dut.out_op.v[1]
+    assert op0 == 5 and op1 == 6
+
+
+if __name__ == '__main__':
+    dut = InputGroup(width=32)
+    vl = verilog.convert(dut, ports=dut.ports())
+    with open("test_inputgroup.v", "w") as f:
+        f.write(vl)
+    run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")