From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Sat, 30 May 2015 15:02:52 +0000 (-0700)
Subject: vk/device: Emit PIPE_CONTROL flushes surrounding new STATE_BASE_ADDRESS
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=33cccbbb738ee71b4b4827707ebd63c791b39d91;p=mesa.git

vk/device: Emit PIPE_CONTROL flushes surrounding new STATE_BASE_ADDRESS

According to the bspec, you're supposed to emit a PIPE_CONTROL with a CS
stall and a render target flush prior to chainging STATE_BASE_ADDRESS.  A
little experimentation, however, shows that this is not enough.  It also
appears as if you have to flush the texture cache after chainging base
address or things won't propagate properly.
---

diff --git a/src/vulkan/device.c b/src/vulkan/device.c
index 13137751a75..87e2e6f85ab 100644
--- a/src/vulkan/device.c
+++ b/src/vulkan/device.c
@@ -2802,8 +2802,23 @@ anv_cmd_buffer_new_surface_state_bo(struct anv_cmd_buffer *cmd_buffer)
    /* Re-emit state base addresses so we get the new surface state base
     * address before we start emitting binding tables etc.
     */
+   anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL,
+                  .CommandStreamerStallEnable = true,
+                  .RenderTargetCacheFlushEnable = true);
    anv_cmd_buffer_emit_state_base_address(cmd_buffer);
 
+   /* It seems like just chainging the state base addresses isn't enough.
+    * If we don't do another PIPE_CONTROL afterwards to invalidate the
+    * texture cache, we still don't always get the right results.  I have
+    * no idea if this is actually what we are supposed to do, but it seems
+    * to work.
+    *
+    * FIXME: We should look into this more.  Maybe there is something more
+    * specific we're supposed to be doing.
+    */
+   anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL,
+                  .TextureCacheInvalidationEnable = true);
+
    return VK_SUCCESS;
 }